V. Chaiyakul, D.D. Gajski, and L. Ramachandran. Minimizing syntactic variance with assignment decision diagrams. Technical Report ICS-TR-92-34, UC Irvine, 1992. Home/Search Document Details and Download
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Coordinated Parallelizing Compiler Optimizations and.. - Gupta, Dutt, Gupta.. (2002) (Correct)
....code required. Nonincremental moves of operations across large blocks of code are possible without visiting each intermediate node [47] Of course, several other representation models such as Value Trace (VT) 49] Yorktown Intermediate format (YIF) 50] Assignment Decision Diagrams (ADDs) [51], Hierarchical Conditional Dependency Graphs (HCDGs) 52] et cetera have been proposed earlier for high level synthesis. Also, Rim et al. 22] and Bergamaschi [53] have proposed new design representation models that attempt to bridge the gap between high level and logic level synthesis and aid in ....
V. Chaiyakul, D.D. Gajski, and L. Ramachandran. Minimizing syntactic variance with assignment decision diagrams. Technical Report ICS-TR-92-34, UC Irvine, 1992.
Speculation Techniques for High Level Synthesis of .. - Gupta, Savoiu.. (2001) (5 citations) (Correct)
....of results. The quality of results for control intensive designs is significantly affected by the control flow in typical applications. The control flow in a design is also affected by the programming style. Some work has focussed on reducing the sensitivity of synthesis to programming style [3, 4]. For effectiveness, a high level synthesis (HLS) system has to make the right tradeoffs among available time, performance, and area costs. Furthermore, the presence of complex control flow significantly effects the quality of synthesis results. In this paper, we propose techniques to move ....
V. Chaiyakul, D.D. Gajski, and L. Ramachandran. Minimizing syntactic variance with assignment decision diagrams. Technical Report ICS-TR-92-34, UC Irvine, 1992.
Hierarchical Conditional Dependency Graphs for Conditional .. - Kountouris, Wolinski (1998) (2 citations) (Correct)
....In [1] 2] several of these problems are addressed. Both rely on special internal representations to cope with syntactic variance. In addition, 1] treats certain cases of conditions defined by inequalities, a subject silently ignored in previous work. In this paper we follow the reasoning of [11], 1] to propose a new internal representation that copes with the syntactic variance at both the mutual exclusiveness identification and scheduling levels. This internal representation is called the Hierarchical Conditional Dependency Graph (HCDG) Using a hierarchical control representation ....
....source code in some standard high level conventional language and the second in using a dataflow specification language supporting clocks, like for instance SIGNAL. Using standard description languages (i.e. C, VHDL, HardwareC etc. necessitates a construction step similar to the one used in [11]. This produces an initial HCDG on which we apply the hierarchization process described in [14] 15] so that redundant clocks are removed and the clock inclusion is refined by finding the maximum hierarchy level for each clock. Using the SIGNAL language a SIGNAL program can be directly compiled ....
V. Chaiyakul, D.D. Gajski, L. Ramachandran, "Minimizing Syntactic Variance with Assignment Decision Diagrams", ICS-TR-92-34, April 1992
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