K.Rath, B. Bose, S.D. Johnson, "Derivation of a DRAM Memory Interface by Sequential Decomposition, Proc. Intl. Conf. on Computer Design - ICCD, IEEE, Oct. 1993, pp.438-441  Home/Search   Document Details and Download   Summary   Related Articles   Check

....possible factorization is shown in Figure 4. We have have investigated several constructive approaches to this family of decompositions [21, 23, 30, 29, 24] We cannot yet claim a universal construction, but we do have transformations general enough to handle many common interface specifications [22]. Performing simultaneous decompositions which is necessary for practical application of formal derivations remains a topic of research. FIB: r, go, in) d , v) r now go u=0 now d u v w 0 A 0 1 A 1 B 0 in 0 1 0 A 1 B T A 1 v F B 0 u 1 w v w Xi ....

Kamlesh Rath, Bhaskar Bose, and Steven D. Johnson. Derivation of a DRAM memory interface by sequential decomposition. In Proceedings of the International Conference on Computer Design (ICCD), pages 438--441. IEEE, October 1993.

....are scheduled in the embedded sequence of transitions such that the implementation relation on the control and datapath are preserved. Our methodology is powerful enough to derive the memory controller for a DRAM memory system, with a protocol specification from DRAM timing diagrams, reported in [21]) 6.3 Data Abstraction Transformations Data abstraction is an important part of the design process, because it enables the designer to reason at the abstract symbolic level before assigning representations to functional units and values in a system. Consider the change of representation for the ....

K. Rath, B. Bose, and S. D. Johnson, "Derivation of a DRAM memory interface by sequential decomposition," in Proceedings of the International Conference on Computer Design, pp. 438-- 441, IEEE, Oct. 1993.

....req Figure 5: machine 2 with allocator state machine between the two state machines and introduce wait loops as part of the communication protocol. In this example we have introduced a protocol in an ad hoc manner; however, our research addresses sequential decomposition formally as discussed in [11]. In the ALLOC state, machine 2 sets the req signal high and waits in an idle loop until the done signal is set by the allocator. Then the new memory and the pointer become available, and execution proceeds with the continuation saved earlier. The allocator is a coprocess waiting in a tight idle ....

K. Rath, B. Bose, and S. D. Johnson, "Derivation of a DRAM memory interface by sequential decomposition, " in Proceedings of the International Conference on Computer Design (ICCD), pp. 438--441, IEEE, Oct. 1993.

No context found.

Kamlesh Rath, Bhaskar Bose, and Steven D. Johnson. Derivation of a DRAM memory interface by sequential decomposition. In Proceedings of the International Conference on Computer Design (ICCD), pages 438--441. IEEE, October 1993.

....machine is incorporated in the original machine. Successive decomposition steps result in an implementation of a network of machines that implement the high level specification. We have used process decomposition to derive a DRAM memory sub system for an implementation of the FM9001 microprocessor [23]. The language described here needs to be extended to allow symbolic values on control ports. The syntax is restricted in order to maintain a simple semantics. There is no mechanism to quantify time in the language. Our approach can provide a framework for both top down and bottom up reasoning by ....

Kamlesh Rath, Bhaskar Bose, and Steven D. Johnson. Derivation of a DRAM memory interface by sequential decomposition. to appear in ICCD, 1993.

No context found.

K.Rath, B. Bose, S.D. Johnson, "Derivation of a DRAM Memory Interface by Sequential Decomposition, Proc. Intl. Conf. on Computer Design - ICCD, IEEE, Oct. 1993, pp.438-441

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC