J. Nestor and D. Thomas, "Behavioral Synthesis with Interfaces," Intl. Conf. on ComputerAided Design, pp.112-115, Nov. 1986.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....iterations. These operations have execution delays that are not known at compile time, or equivalently, their delays are unbounded. Second, real time ASIC applications require the specification of detailed timing constraints in the hardware model and their enforcement in the synthesis process [14] [15] 16] Timing constraints specify upper and lower bounds on the time separation between two operations. They can be applied, for example, to control the time gap between a read and a write of an external bus, or to synchronize two write operations. We present in this paper a scheduling ....

....due to the assignment of multiple operations to a single module has already been resolved by introducing sequencing dependencies between these operations. This is in contrast to heuristic approaches that combine scheduling with module binding [8, 10, 12] or perform module binding after scheduling [5, 4, 14]. Several high level synthesis systems use variations of this general model [18, 6, 8, 2] In particular, the Hercules Hebe high level synthesis system [17, 19] represents the hardware model by a polar hierarchical acyclic graph, where the vertices represent operations to perform and the edges ....

J. Nestor and D. Thomas, "Behavioral synthesis with interfaces," in Proceedings of the Design Automation Conference, pp. 112-115, June 1986.

....Section 3 gives a formal definition of soft scheduling. Section 4 describes threaded scheduling algorithm and proves its correctness, optimality and linearity. Section 5 gives the experimental results. 2 Related Works Traditional HLS tools or VLIW compilers [1] typically use list scheduling [2] and force directed scheduling [3] or their variants for resource constrained and timing constrained scheduling. Relative scheduling [4] has the additional capability of scheduling operations with undeterministic delay. Pathbased scheduling [5] percolation scheduling , and trace scheduling ....

J. Nestor and D.E Thomas. Behavioral Synthesis with Interfaces. Proceedings of the IEEE Conference on Computer Aided Design, November 1986.

....interface timing relationships with state machines. While state machines are useful for describing series of interface actions as they occur in practice, they cannot efficiently represent protocols in which several independent series of events happen in parallel. However, the BSI ISPS language [NT86] allowed true partial orderings of events by attaching labels to events and allowing simple timing constraints to be expressed between them. These constraints were of the form found in Equations 3.1 or 3.2. Additionally, although these early interface descriptions were written to describe ....

J. Nestor and D. Thomas. Behavioral synthesis with interfaces. In Proceedings of the International Conference on Computer-Aided Design, November 1986.

....in the multiprocessor environment. Such an overhead is called the communication cost. We assume that the communication cost is proportional to the transmitted data volume and that all processors are fully connected through multiple channels. In this paper, we modify a list scheduling algorithm [3, 7] to work according to the imposed communication cost environment. Our rotation technique is responsible for improving such a schedule by parallelizing the tasks represented as nodes in the DFG without violating the dependence and communication constraints. An example consists of a set of four ....

J. Nestor and D.E. Thomas, "Behavioral Synthesis with Interfaces". Proc. of ICCAD, 1986, pp. 112-115.

....methodology which generates circuits that behave correctly even in the presence of variations on gate and wire delays. However it is not always possible to neglect timing information corresponding to either internal circuit delays or constraints on the environment for proper circuit operation [12]. This is particularly true in the design of microprocessor based systems whose protocols are required to meet hard deadlines. For this purpose we use an interpreted timed Petri net which allows us to reason about operational circuit delays and environmental timing constraints. Our model is ....

....[16, 1] STG s were first applied to the design of delay insensitive circuits which assumes unbounded wire and gate delays. Although a very powerful design concept, delay insensitivity is not realistic for describing the behavior of microprocessor components. Pioneering work by Nestor and Thomas [12] identified the necessity of dealing with timing constraints in the design of interfaces. Recently some work has been done in extending STG s to model circuit delays. Myers and Meng [11] used a conservative estimate of gate delays and available environmental timing constraints to remove links of ....

J. A. Nestor and D. E. Thomas, "Behavioral synthesis with interfaces," in Proc. ICCAD, pp. 112--115, 1986.

....in most cases. 1 Introduction This paper presents TCLP, a methodology to solve TimeConstrained Loop Pipelining. TCLP is NP complete [3] Two types of timing constraints (TCs) have been considered in the literature: local TCs to specify minimum and or maximum TCs between operation pairs [11], and global TCs to specify a maximum delay time to process a set of data. The term TCs has been previously used to refer to both local and global TCs, despite they are completely different. Approaches to solve scheduling with local TCs can be found in [7, 10, 11] On the other hand, some Integer ....

....maximum TCs between operation pairs [11] and global TCs to specify a maximum delay time to process a set of data. The term TCs has been previously used to refer to both local and global TCs, despite they are completely different. Approaches to solve scheduling with local TCs can be found in [7, 10, 11]. On the other hand, some Integer Linear Programming (ILP) approaches have been proposed to solve scheduling (not loop pipelining) with global TCs [1, 5] Force Directed Scheduling [12] solves both local and global TCs. This paper addresses loop pipelining with global TCs. Henceforth, we will ....

J. Nestor and D.E. Thomas. Behavioral synthesis with interfaces. In Proc. Int. Conf. Computer-Aided Design, pages 112--115, November 1986.

....has been a lot of work on scheduling of acyclic data flow graphs for high level synthesis systems. Many variations of the common scheduling algorithms introduced in Section 1.1 are adopted in these systems. Especially, list scheduling is used by many systems under different priority functions [32, 57, 61]. Some typical priority functions are as late as possible time, the number of descendants, and the difference between as soon as possible and as late as possible times (mobility) 61] Several scheduling algorithms are compared in [37] Force directed scheduling [67] uses the probability ....

Nestor, J., and Thomas, D. E. Behavioral synthesis with interfaces. In Proceedings of the International Conference on Computer Aided Design (Nov. 1986), pp. 112--115.

....this time interval the communication cost. We assume that the communication cost is proportional to the transmitted data volume and that all processors are fully connected through multiple channels (so that no data transmission conflicts occur) In this paper, we modify a list scheduling algorithm [3,4,9] to be used to schedule a group of tasks according to the imposed communication cost environment. Our rotation technique is responsible for improving such a schedule by parallelizing the tasks represented as nodes in the DFG without violating the dependence and communication constraints. An ....

J. Nestor and D. E. Thomas, "Behavioral Synthesis with Interfaces". Proceedings of the International Conference on Computer Aided Design, Nov, 1986, pp. 112-115.

....process formalisms (e.g. 54, 30] It is typical that an area of verification research would have this orientation, and also that the top down view would be better represented in synthesis research. In addition to Boriello s work [4] approaches to scheduling by Ku, Micheli [47] and Nestor et.al [62] have considered protocol like constraints. 2.1. FORMAL METHODS 9 Kurshan uses L automata with language and process homomorphism [49] to verify reactive systems by stepwise reduction and refinement. He uses a bottom up model with registers and controllers as processes at the lowest level and ....

J. A. Nestor and D. Thomas. Behavioral synthesis with interfaces. In Proceedings of ICCAD, November 1986.

....these results are communicated to and from the external environment. Of critical importance are the analysis and synthesis of the interfaces between the processes and the protocol governing their interaction, as well as their efficient implementation on shared physical media. With few exceptions [5, 6, 7, 8, 9], existing techniques do not adequately address the synthesis of communication for concurrent systems. This paper presents a methodology for the analysis and synthesis of interfaces for time constrained concurrent systems. Such systems are characterized by tightly interacting processes operating ....

J. Nestor and D. Thomas, "Behavioral synthesis with interfaces, " in Proceedings of the Design Automation Conference, pp. 112--115, June 1986.

....FPGAs where the number of interconnections between partitions is minimized. Combinational Logic FF 4 Both heuristic and exact algorithms were used to solve the scheduling problem in high level synthesis. Numerous heuristics were proposed for this problem including transformational [15] list [16], force directed [17] and graphtheoretical approaches [18] Exact algorithms were also proposed to solve the problem based on integer programming formulations [9] However, these formulations were derived in an ad hoc manner. New results from the polyhedral theory of integer linear programming ....

J. Nestor and D. Thomas, "Behavioral Synthesis with Interfaces," Proc. Internactional Conference on Computer-Aided Design, 1986, pp. 112-115.

....formalisms (e.g. 20, 9] It is typical that an area of verification research would have this orientation, and also that the top down view would be better represented in synthesis research. In addition to Boriello s work (cited above) approaches to scheduling by Ku, Micheli [17] and Nestor et.al [22] have considered protocol like constraints. Dill et.al have used a B uchi automata based model to verify safety and liveness properties using language containment [7] McMillan and Dill have also modelled timing constraints as min max constraints and used a generalized branch and bound algorithm ....

J. A. Nestor and D. Thomas. Behavioral synthesis with interfaces. In Proceedings of ICCAD, November 1986.

....encapsulating the operators in the light gray rectangle in Fig. 8 into a separate process. Section B describes the transformations required to split the VT vertically, encapsulating the operators in the dark gray oval into a separate process. Synthesis results from the CSTEP control step scheduler [11, 6] and the EMUCS data path allocator [11] are presented for all designs. A. A Two Process Filter This section describes the transformations required to interactively split the filter s VT horizontally into two processes, gives synthesis results for the single process and two process designs, and ....

J.A. Nestor and D.E. Thomas. Behavioral Synthesis with Interfaces. In Proc. of ICCAD-86, pages 112--115. IEEE, Santa Clara, California, November, 1986.

....and the IIT Education Research Initiative Fund. To appear in IEEE Transactions on CAD, May 1993 (Tentative) 2 the various hardware resources used during allocation. Second and equally important, it fixes the relative timing of operators and thus the satisfaction of timing constraints. [2,3]. Timing constraints are important because they allow designers to specify both desired performance and interface information [2,4] Fig. 1 illustrates the scheduling problem using a typical CDFG, which is a directed graph in which nodes represent operators and edges represent ordering ....

....hardware resources used during allocation. Second and equally important, it fixes the relative timing of operators and thus the satisfaction of timing constraints. 2,3] Timing constraints are important because they allow designers to specify both desired performance and interface information [2,4]. Fig. 1 illustrates the scheduling problem using a typical CDFG, which is a directed graph in which nodes represent operators and edges represent ordering dependencies between operators. 1 Source and sink nodes represent the beginning and end of activities in the graph. Edges between nodes ....

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J. Nestor and D. Thomas, "Behavioral Synthesis with Interfaces", Proceedings ICCAD-86, pp. 112-115, Nov. 1986.

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J. Nestor and D. Thomas, "Behavioral Synthesis with Interfaces," Intl. Conf. on ComputerAided Design, pp.112-115, Nov. 1986.

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J. A. Nestor and D. E. Thomas, "Behavioral synthesis with interfaces," in Proceedings of the International Conference on Computer-Aided Design, pp. 112--115, 1986.

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