B. Bishop, T. Kelliher, and M. Irwin. The Design of a Register Renaming Unit. In Proc. of Great Lakes Symposium on VLSI, 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....N A N A BTB 1K entry 512 entry 32 entry 2 way 4 way Return address stack 32 entry N A N A Memory Hierarchy L1 Dcache Size 64K 8K 32K L1 Dcache Assoc. 2 way 2 way 2 way L1 Icache Size 64K 8K 32K L1 Icache Assoc. 2 way 4 way 2 way DTLB Size (full asset) 128 64 64 ITLB Size (full asset) 128 32 64 Process Specifications Vdd 2.2V 3.3V 3.3V MHz 600 200 200 Table 6: Configuration of Processors In this section we perform a third form of validation in which we compare the published maximum power numbers for three commercial microprocessors with the values produced by our models for ....

....2 way 4 way Return address stack 32 entry N A N A Memory Hierarchy L1 Dcache Size 64K 8K 32K L1 Dcache Assoc. 2 way 2 way 2 way L1 Icache Size 64K 8K 32K L1 Icache Assoc. 2 way 4 way 2 way DTLB Size (full asset) 128 64 64 ITLB Size (full asset) 128 32 64 Process Specifications Vdd 2. 2V 3.3V 3.3V MHz 600 200 200 Table 6: Configuration of Processors In this section we perform a third form of validation in which we compare the published maximum power numbers for three commercial microprocessors with the values produced by our models for similar configurations. This allows us ....

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B. Bishop, T. Kelliher, and M. Irwin. The Design of a Register Renaming Unit. In Proc. of Great Lakes Symposium on VLSI, 1999.

.... Two of the larger complex logic blocks that we consider are the instruction selection logic (in the instruction window) and the dependency check logic (in the register renaming unit) We model circuit structures based on the selection logic described in [21] and the dependency check logic in [3]. We model the power consumption of result buses by estimating the length of the result buses using the same assumptions about functional unit height made in [22] These lengths are multiplied by the metal capacitance per unit length. This equation is shown in Table 1. Modeling the power ....

B. Bishop, T. Kelliher, and M. Irwin. The Design of a Register Renaming Unit. In Proc. of Great Lakes Symposium on VLSI, 1999.

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