N. P. Jouppi, J. Bertoni, and D. W. Wall. A unified vector /scalar floating-point architecture. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pages 134-- 143, Boston, Massachusetts, Apr. 3--6, 1989. ACM SIGARCH, SIGPLAN, SIGOPS, and the IEEE Computer Society.  Home/Search   Document Not in Database   Summary   Related Articles

....offers a single register file with 32768 registers, each register being 64bit wide. This organization is similar to the unified 4 MANEL FERN ANDEZ AND ROGER ESPASA DIXIE: A RETARGETABLE BINARY INSTRUMENTATION TOOL vector scalar register file provided by the MultiTitan architecture [5]. There is no distinction between floating point and integer registers as is usually the case with most other instruction sets. The large number of registers is required to accommodate vector instructions. The register file can be viewed as a collection of vector registers with variable length. ....

N. P. Jouppi, J. Bertoni, and D. W. Wall. A unified vector /scalar floating-point architecture. In Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pages 134-- 143, Boston, Massachusetts, Apr. 3--6, 1989. ACM SIGARCH, SIGPLAN, SIGOPS, and the IEEE Computer Society.

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