Jyh-Charn Liu and Hung-Ju Lee. Deterministic upperbounds of the worst-case execution times of cached programs. In Proceedings of the 15th Real-Time Systems Symposium, pages 182--191, December 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the time used by the execution of B. We assume that each # B is invariable, i.e. the timing behavior of a basic block does not change if it is executed several times. This excludes e#ects of caching or pipelining from our model. Some research on this subject has been conducted (cf. HBW94, HWH95, LL94, AMWH94] but these issues are out of the scope of this paper. In [BFS00] cache hit analysis is performed with help of symbolic evaluation. The data flow framework defined below will allow for estimating the overall timing behavior of a procedure by employing solution algorithms well known for ....

J.C. Liu and H.J. Lee, Deterministic upperbounds of the worst-case execution times of cached programs, Proc. of the Fifteenth IEEE Realt-Time Systems Symposium (1994), 182--191. 8

....of B. We assume that each B is invariable, i.e. the timing behavior of a basic block does not change if it is executed several times. This excludes effects of caching or pipelining from our model. Some research on this subject has been conducted (cf. Harmon et al. 1994; Healy et al. 1995; Liu and Lee, 1994; Arnold et al. 1994) but these issues are out of the scope of this paper. In (Blieberger et al. 2000b) cache hit analysis is performed with help of symbolic evaluation. The data flow framework defined below will allow for estimating the overall timing behavior of a procedure by employing ....

Liu, J. and H. Lee: 1994, `Deterministic Upperbounds of the Worst-Case Execution Times of Cached Programs'. Proc. of the Fifteenth IEEE Realt-Time Systems Symposium pp. 182--191.

....hold instructions and data is called a mixed or unified cache. Cache design has been extensively studied. Good surveys can be found in (Alt et al. 1996; Mueller, 1997; Ottosson and Sjoedin, 1997; Li et al. 1996; Li et al. 1995; Healy et al. 1995; Arnold et al. 1994; Nilsen and Rygg, 1995; Liu and Lee, 1994; Hennessy and Patterson, 1990) 3. Symbolic Evaluation Symbolic evaluation 3 (Cheatham et al. 1979; Ploedereder, 1980; Fahringer and Scholz, 1997; Fahringer and Scholz, 1999) z is a constructive description of the semantics of a program. Moreover, symbolic evaluation is not merely an ....

....in real time systems (Park, 1993; Puschner and Koza, 1989; Chapman et al. 1996) was far too complex. Recent research (Arnold et al. 1994) has proposed methods to estimate tighter bounds for WCET in systems with caches. Most of the work has been successfully applied to instruction caches (Liu and Lee, 1994) and pipelined architectures (Healy et al. 1995) Lim et al. 1994) extend the original timing schemas, introduced by Puschner and Koza (1989) to handle pipelined architectures and cached architectures. Nearly all of these methods rely on frequency annotations of statements. If the programmer ....

Liu, J. and H. Lee: 1994, `Deterministic Upperbounds of the Worst-Case Execution Times of Cached Programs'. In: Proc. of the IEEE Real-Time Systems Symposium. pp. 182--191.

....Analysis techniques which do not consider the cache, e.g. PK89, PS91, Gus94, CBW94, PK95, LM95] are not able to provide tight estimations of WCET for cached systems. Recently, researchers have proposed methods which allow tighter estimation of WCET in systems which use caches, e.g. AMWH94, LL94, LBJ 95, KMH96, LMW96] Arnold et.al. AMWH94] consider only instruction caches which partly limits the applicability of their analysis. Lim et.al. LBJ 95] extend the original timing schemas, proposed by Puschner and Koza [PK89] to handle pipelined and cached architectures. Kim, Min and ....

....the possibility to express semantical dependencies in the code. For instance, it is very hard to express that the number of iterations in an inner loop is dependent on the loop index of an outer loop, or that two sub paths at different locations in the code are mutually exclusive. The method in [LL94] suffers from similar problems. In recent work Li, Malik and Wolfe [LMW96] revise the work in [LM95] on which our work too is based) and the Implicit Path Enumeration Technique (IPET) is extended to allow pipeline execution and cache memory to be modeled with linear constraints. In IPET [LM95] ....

J-C. Liu and H-J. Lee. Deterministic upperbounds of the worst-case execution time of cached programs. In Proc. 15 th Real-Time Systems Symposium, pages 182--191, December 1994.

....a RISC processor, however, the calculation of a tight WCET bound of a program involves difficulties that come from the very characteristics of RISC processors: pipelined execution and instruction data caching. Recently there has been much progress in worst case timing analysis for RISC processors [2, 5, 7, 10, 11, 13, 14]. However, most of the previous studies focused mainly on the timing analysis of pipelined execution and instruction caching, while largely ignoring the data caching effects [2, 5, 10, 13, 14] Even the approaches that do consider the timing effects of data caching have severe restrictions. For ....

....caching. Recently there has been much progress in worst case timing analysis for RISC processors [2, 5, 7, 10, 11, 13, 14] However, most of the previous studies focused mainly on the timing analysis of pipelined execution and instruction caching, while largely ignoring the data caching effects [2, 5, 10, 13, 14]. Even the approaches that do consider the timing effects of data caching have severe restrictions. For example, the technique explained in [11] requires that the addresses of references from each program construct be fixed. For instruction block 1 references, such a requirement is satisfied for ....

J.-C. Liu and H.-J. Lee. Deterministic Upperbounds of the Worst-Case Execution Times of Cached Programs. In Proceedings of the 15th Real-Time Systems Symposium, pages 182--191, 1994.

....paths, and accurate pipeline analysis are equally important in determining tight estimated WCETs. Thus, a good cache analysis method needs to integrate these capabilities while at the same time be capable of handling different kinds of cache organizations. 2. Related Work Several research groups [2, 7, 8] have proposed different WCET analysis methods with direct mapped instruction cache modeling. The main drawback of the above approaches is that the number of iterations of all loops in the program is assumed to be fixed for each loop entry, and it is not possible to utilize any additional ....

J.-C. Liu and H.-J. Lee. Deterministic upperbounds of the worst-case execution times of cachedprograms. In Proceedings of the 15th IEEE Real-Time Systems Symposium, pages 182--191, December 1994.

....used to obtain such bounds. Measurement based techniques are, in many cases, inadequate to produce a timing estimation for real time systems since their predictions are usually not guaranteed, or enormous cost is needed. Due to these limitations, analytical approaches are becoming more popular [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Many of these analytical studies, however, consider a simple machine model, thus largely ignoring the timing effects of pipelined execution and cache memory [8, 12, 13, 15] A. Timing Analysis of Pipelined Execution The timing effects of pipelined execution have been recently studied by Harmon, ....

....types of cache miss cannot be avoided if the cache has a limited size and or set associativity. Among the analytical WCET prediction schemes that we are aware of, only four schemes take into account the timing variation resulting from intra task cache interference (three for instruction caches [10, 9, 7] and one for data caches [14] The static cache simulation approach which statically predicts hits or misses of instruction references is due to Arnold, Mueller, Whalley and Harmon [10] In this approach, instructions are classified into the following four categories based on a data flow ....

[Article contains additional citation context not shown here]

J.-C. Liu and H.-J. Lee, "Deterministic Upperbounds of the Worst-Case Execution Times of Cached Programs," in Proceedings of the 15th Real-Time Systems Symposium, pp. 182--191, 1994.

....have to be applied to make those processors more predictable. With caches, a good first step to increase processor utilization is to calculate the worst case execution time (WCET) of tasks taking into account the cache speed up. Some tools can be used to estimate the WCET of cached programs [1] 13][15]. These tools typically assume continuity for the code execution, thus no preemption is allowed. This limitation restricts the application of such tools to non preemptive scheduling policies like cyclic 2 executives or cooperative scheduling. However, two actions can be undertaken to make caches ....

J. Liu and H. Lee."Deterministic Upperbounds of the Worst-Case Execution Time of Cached Programs". IEEE Real-Time Systems Symposium, pages 182-191, 1994.

....cannot be avoided if the cache has a limited size and or set associativity 3 and make it difficult to accurately predict the WCET of a task due to the cyclic dependency explained earlier. Recently substantial progress has been made in this area and interested readers are referred to [2] 16] [17], 19] Inter task interference is caused by task preemption. When a task is preempted, most of its cache blocks are displaced by the newly scheduled task and the tasks scheduled thereafter. When the preempted task resumes execution, it requests the previously displaced blocks and experiences a ....

J.-C. Liu and H.-J. Lee. Deterministic upperbounds of the worst-case execution times of cached programs. In Proceedings of the 15th Real-Time Systems Symposium, pages 182--191, 1994.

....to 1. In the formula, a=0 for a direct mapped cache, a=0.5 for two way set associative and a=1 for four way set associative. M A r s r s 3 07 075 1 10 2 25 3 3 2 . a Recently some papers have been presented to estimate the WCET of cached programs [23][21] 29] 3] The last two references propose a static method capable of predicting conservatively around 70 of cache hits. However, we have chosen the model presented in [12] for several reasons. Firstly, it takes into account the factors we intend to include in the experiments in an analytical ....

J.Liu and H.Lee. "Deterministic Upperbounds of the Worst-Case Execution Time of Cached Programs". IEEE Real-Time Systems Symposium, pages 182-191, 1994.

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Jyh-Charn Liu and Hung-Ju Lee. Deterministic upperbounds of the worst-case execution times of cached programs. In Proceedings of the 15th Real-Time Systems Symposium, pages 182--191, December 1994.

No context found.

J.-C. Liu and H.-J. Lee. Deterministic upperbounds on the worst-case execution time of cached programs. In IEEE Real-Time Systems Symposium, Dec. 1994.

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J. Liu and H. Lee, Deterministic Upperbounds of the Worst-Case Execution Times of Cached Programs, IEEE Real-Time System Symposium, Dec. 1994.

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