R. Jain et al, "Module Selection for Pipelined Synthesis "Proc. Design Automation, Anaheim, pp. 542-547, 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....because the hardware units can be used more efficient. FDS can in this environment be used to allocate the hardware units. FDLS and FDS presume a previous type assignment for all operations and do not allow component types with intersecting functionality in one circuit. In the SEHWA system [JaPP88] PaPa86] effort is spent to select the component types by analyzing the area time design space. This type selection is performed at the first step during the data path synthesis and precedes the allocation of the number of components. This allows a trade off to use e.g. fast or slow adders in ....

....types number of overall iterations (PROC 1) 5 Examples and results From the literature two filter examples were selected. The 5th order filter [DeDN85] contains 26 additions and 8 multiplications. The control flow consists of one single loop without mutual exclusive operations. The AR filter [JaPP88] contains 12 additions and 16 multiplications with also a single loop as control flow. Table 1 contains the available component types for the additions and the multiplications. It contains adders and multipliers and also some ALUs for both operations. The properties were estimated on the base of ....

R. Jain, A. Parker, N. Park, "Module Selection for Pipelined Synthesis", 25 th Design Automation Conference, 1988

....to be considered is the loop body of the HAL example [20] all operands with 16 bit width) The example has a total area of 4,384 cells and a critical path delay of 58 cycles. The results presented in Table 1 show small improvements of the SA over the ELS. The 2 nd example is the AR filter [21]. It has 16 multipliers and 12 adders contributing to a total area of 16,960 cells and a critical path delay of 90 cycles (all operands with 16 bit width) The results are shown in Table 2. Table 1. Results for the HAL example (t cycles =2; A: MaxArea = 2,457; B: MaxArea = 4,096) CASE #Part ....

R. Jain, A. Parker, N. Park, "Module Selection for Pipelined Synthesis, " in Proc. 25 th Design Automation Conference, 1988, 542-547.

....explained in greater detail in Section 4, 5 and 6. Finally, we present experimental results and give conclusions. 2 Previous Work Several previous papers addressed the issue of clock period estimation for a given data flow graph. For example, there are several clock estimation schemes [7] 6] [4] that use the delay of the slowest component as the estimated clock period. However, using the slowest component delay as the clock period can lead to under utilized functional units in cases where the components have widely differing delays. A clock estimation method based on slack minimization ....

....our results with related research in clock selection; instead, we have utilized force directed scheduling, which is a well known time constrained scheduling algorithm. This experiment is conducted on four examples that are typically implemented as pipelined designs: the AR lattice filter (AR) [4], the linear phase b spline interpolated filter (BSpline) 5] the elliptical filter (EF) and the HAL benchmark. For each of the examples, we first generate a number of input descriptions by manually pipelining the specification into a different number of stages. For example, we pipeline the ....

R. Jain, A. C. Parker, and N. Park, "Module Selection for Pipelined Synthesis," in Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988.

....solvers. Many problem solving techniques, e.g. min max search with alpha beta pruning [50] are dependent on having good estimation functions. Work on the development and learning of estimation functions includes the early work of Samuels in checkers [50] and the more recent work in VLSI of Jain [26, 27, 25], Kucukcakar [34] and McFarland [42] The FDO research complements this body of work in that it focusses on developing methods for correcting inefficiencies a posteriori that could not be detected with estimation functions. These inefficiencies could not be detected because they are either (1) ....

....amongst four clusters as evenly as possible. The result of each clustering is represented by the number on the right of the pairings. The dashed line on the right (the cut line) shows the partitioning of the 16 points into four clusters. The first cluster is at 55 and is composed of the points [55,53,27,23]. The other three clusters are: 2) 51 with [51,18,17,40] 3) 50 with [50,48,46,38] and (4) 42 with [42,36,33,21] Cluster 0 left 0 right 3 Cluster 1 left 4 right 7 Cluster 2 left 8 right 11 Cluster 3 left 12 right 15 Figure 4.28: Seed cluster indices find hw cluster( saves the results of ....

Rajiv Jain, Alice Parker, and Nohbyung Park. Module selection for pipelined synthesis. In Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988.

....the Volume, DHRC and AR examples. In this experiment, we present the range of designs obtained by pipelining a system and partitioning it amongst hardware and software components. We present results for the Volume System [7] the differential heat release computation (DHRC) 3] and the AR Filter [12]. The Volume system specification contains 14 leaf behaviors, while the DHRC and AR examples, contain just one leaf behavior each. We place a set of different PS delay constraints on each of the examples, and our algorithm returns a set of designs, ranging from all hardware, highly pipelined ....

Rajiv Jain, Alice Parker, and Nobhyung Park. Module selection for pipelined synthesis. In Proceedings of the 25th Design Automation Conference, pages 542--547, 1988.

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R. Jain et al, "Module Selection for Pipelined Synthesis "Proc. Design Automation, Anaheim, pp. 542-547, 1988.

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