W. Damm, A. Pnueli, and S. Ruah, "Herbrand automata for hardware verification," 9th International Conference on Concurrency Theory (CONCUR '98), SpringerVerlag, September, 1998. Home/Search Document Details and Download
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Processor Verification Using Efficient Reductions of the.. - Bryant, German, Velev (1999) (10 citations) (Correct)
....in [BDL96] Burch and Dill s work has generated considerable interest in the use of uninterpreted functions to abstract data operations in processor verification. A common theme has been to adopt Boolean methods, either to allow integration of uninterpreted functions into symbolic model checkers [DPR98, BBCZ98], or to allow the use of Binary Decision Diagrams (BDDs) Bry86] in the decision procedure [HKGB97, GSZAS98, VB98] Boolean methods allow a more direct modeling of the control logic of hardware designs and thus can be applied to actual processor designs rather than highly abstracted models. In ....
....the efficiency gains possible with p terms. In our processor model, we can abstract register identifiers as unrestricted terms, while modeling program data and instruction data as p terms. As a result, our verifications cover designs with arbitrarily many registers. In contrast, both [BBCZ98] and [DPR98] used bit encodings of register identifiers and were unable to scale their verifications to a realistic number of registers. In a recent paper, Pnueli, et al. PRSS99] also propose a method to exploit the polarity of the equations in a formula containing uninterpreted functions with equality. They ....
[Article contains additional citation context not shown here]
W. Damm, A. Pnueli, and S. Ruah, "Herbrand automata for hardware verification," 9th International Conference on Concurrency Theory (CONCUR '98), SpringerVerlag, September, 1998.
Exploiting Positive Equality in a Logic of Equality with.. - Bryant, German, Velev (1999) (19 citations) (Correct)
....[NO80] Burch and Dill s work has generated considerable interest in the use of uninterpreted functions to abstract data operations in processor verification. A common theme has been to adopt Boolean methods, either to allow integration of uninterpreted functions into symbolic model checkers [DPR98,BBCZ98], or to allow the use of Binary Decision Diagrams in the decision procedure [HKGB97,GSZAS98,VB98] Boolean methods allow a more direct modeling of the control logic of hardware designs and thus can be applied to actual processor designs rather than highly abstracted models. In addition to ....
....of the unrestricted functional terms of Burch and Dill while exploiting the efficiency gains possible with p terms. In our processor model, we can abstract register identifiers as unrestricted terms, while modeling program data and instruction data as p terms. In contrast, both [BBCZ98] and [DPR98] used bit encodings of register identifiers and were unable to scale their verifications to a realistic number of registers. In a different paper in this proceedings, Pnueli, et al. [PRSS99] also propose a method to exploit the polarity of the equations in a formula containing uninterpreted ....
[Article contains additional citation context not shown here]
W. Damm, A. Pnueli, and S. Ruah, "Herbrand automata for hardware verification," 9th International Conference on Concurrency Theory CONCUR '98, SpringerVerlag, September, 1998.
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