P. Breuer, L. Fernandez & C. Delgado Kloos, " A simple denotational semantics, Proof theory and a validation condition generator for unit-delay VHDL", Formal Methods in System Design, Volume 7, August 96.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....computer aided design tools; to the implementation of language processors; and for formal reasoning about VHDL descriptions. Furthermore, this exercise will enhance our understanding of the various VHDL 93 constructs features. There have been a number of proposals for a formal semantics of VHDL [1, 3 8, 12 18, 20], many of them dealing with unit delay subsets of VHDL 87. To facilitate formal verification, Belhadj et al. 1] specify VHDL 87 attributes involving time in SIGNAL language. Petri nets are used to specify the semantics of a VHDL 87 subset in [4, 6, 13] Van Tassel [18] mechanizes reasoning ....

....subsets of VHDL 87. To facilitate formal verification, Belhadj et al. 1] specify VHDL 87 attributes involving time in SIGNAL language. Petri nets are used to specify the semantics of a VHDL 87 subset in [4, 6, 13] Van Tassel [18] mechanizes reasoning about Femto VHDL in HOL, while Breuer et al. [3] develop # http: www.cs.wright.edu tkprasad. 70 THIRUNARAYAN AND EWING denotational semantics for a unit delay VHDL 87 subset. Deharbe and Borrione [5] give operational semantics for a VHDL 87 subset that excludes quantitative timing information (among other things) in terms of abstract ....

P. Breuer, L. Sanchez, and C.D. Kloos, "A simple denotational semantics, proof theory and validation condition generator for unit delay VHDL," Formal Methods in System Design, Vol. 7, No. 1/2, 1995, pp. 27--51.

....computer aided design tools; to the implementation of language processors; and for formal reasoning about VHDL descriptions. Furthermore, this exercise will enhance our understanding of the various VHDL 93 constructs features. There have been a number of proposals for a formal semantics of VHDL [1, 3, 4, 5, 6, 8, 7, 12, 13, 14, 15, 16, 17, 18, 19], many of them dealing with unit delay subsets of VHDL 87. To facilitate formal verification, Belhadj et al. [1] specify VHDL 87 attributes involving time in SIGNAL language. Petri nets are used to specify the semantics of a VHDL 87 subset in [4, 6, 13] Van Tassel [18] mechanizes reasoning about ....

....subsets of VHDL 87. To facilitate formal verification, Belhadj et al. [1] specify VHDL 87 attributes involving time in SIGNAL language. Petri nets are used to specify the semantics of a VHDL 87 subset in [4, 6, 13] Van Tassel [18] mechanizes reasoning about FemtoVHDL in HOL, while Breuer et al. [3] develop denotational semantics for a unit delay VHDL 87 subset. Deharbe and Borrione [5] give operational semantics for a VHDL 87 subset that excludes quantitative timing information (among other things) in terms of abstract machines, while Goossens [8] defines structural operational semantics ....

Breuer, P., Sanchez, L., and Kloos, C. D., "A simple denotational semantics, proof theory and validation condition generator for unit delay VHDL", Formal Methods in System Design, 7(1-2), August 1995.

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P. Breuer, L. Fernandez & C. Delgado Kloos, " A simple denotational semantics, Proof theory and a validation condition generator for unit-delay VHDL", Formal Methods in System Design, Volume 7, August 96.

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