F.F. Dragan, A.B. Kahng, I.I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably good global buffering using an available buffer block plan", Proc. ICCAD, 2000, pp. 104--109.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....in their objective function. Tang and Wong [10] proposed an optimal algorithm to assign buffers to buffer blocks assuming that only one buffer is needed per net. In the paper [11] a realistic global router is used to evaluate congestion of each candidate placement solution. Dragan et al. [5] use a multicommodity flow based approach to allocate buffers to some pre existing buffer blocks such that the required upper and lower bounds on buffer intervals can be satisfied as much as possible. Alpert et al. 1] make use of tile graph and dynamic programming to perform buffer block ....

....estimation on the interconnect information. In our model, we assume that buffers are constrained to be inserted for long enough wires such that the distance between adjacent buffers is lying within a range [low; up] given by the user. We call this the variable interval buffer insertion constraint [5, 1]. For example, according to [7] global repeater rules for a high end microprocessor design in 0.25 m CMOS requires repeaters at intervals of at most 4500 m, and we can model this situation by assigning the low and up appropriately. In our floorplanner, we will divide a floorplan into a ....

F. F. Dragan, A. B. Kahng, S. Muddu, and A. Zelikovsky. Provably good global buffering using an available buffer block plan. In Proc. Int. Conf. On CAD, 2000.

....techniques to achieve timing closure. It was projected that over 700K repeaters will be inserted on a single chip in the 70 nm technology [3] In current practices, buffers are inserted after routing. However buffers also take up silicon resources (40 Theta to 200 Theta minimum inverter size [5]) and cannot be inserted wherever we want. A good planning of the module positions during the floorplanning stage so that buffers can be inserted wherever needed in the later routing stages will be very useful. Besides, buffers also contribute delay and area, and their locations should be ....

....in their objective function. Tang and Wong [12] propose an optimal algorithm to assign buffers to buffer blocks assuming that only one buffer is needed per net. In the paper [13] a realistic global router is used to evaluate the congestion of each candidate placement solution. Dragan et al. [5] use a multi commodity flow based approach to allocate buffers to some pre existing buffer blocks such that the required upper and lower bound on buffer intervals can be satisfied as much as possible. Alpert et al. 1] make use of tile graph and dynamic programming to perform buffer block ....

[Article contains additional citation context not shown here]

F. F. Dragan, A. B. Kahng, S. Muddu, and A. Zelikovsky. Provably good global buffering using an available buffer block plan. In Proceedings of IEEE Internation Cnference on Computer-Aided Design, pages 104--109, 2000.

....et al. 12] add in the notion of independence to feasible regions so that these regions for different buffers of a net can be computed independently. Tang and Wong [14] propose an optimal algorithm to assign buffers to buffer blocks assuming that only one buffer is needed per net. Dragan et al. [7] use a multicommodity flow based approach to allocate buffers to some pre existing buffer blocks. Alpert et al. 2] make use of tile graph and dynamic programming to perform buffer block planning. Finally, Lou et al. 10] apply probabilistic analysis to estimate congestion and routability, and ....

S. M. F. F. Dragan, A. B. Kahng and A. Zelikovsky. Provably good global buffering using an available buffer block plan. In Proc. Int. Conf. On CAD, 2000.

....approach, buffers are clustered together as a buffer block to facilitate floorplan and routing. Cong et al. 5] Tang and Wong[12] and Sarkar et al. 11] proposed algorithms for buffer block planning problem to minimize the chip area and the number of buffer blocks. In two recent works, Dragan et al.[7][8] gave algorithms for global buffered routing problem with fixed pins. Their work is based on multicommodity flow which is an NP hard problem. In this paper, we address the problem of simultaneous Pin assignment and Buffer planning (PB) for a given buffer block plan. Our algorithm uses min cost ....

F.F. Dragan, A.B.Kahng, I.I. Mandoiu, S. Muddu, and A. Zelikovsky, "Provably good global buffering using an available buffer block plan", Proc. ICCAD, pp. 104-109, 2000.

....buffer block layouts of the MCNC circuit xerox by (a) RDM RES and (b) BBP FR. The ten big blocks are circuit functional modules and the rest are buffer blocks. The recent work by [28] studied the BBP under simultaneous delay and transition time constraints. Given an existing buffer block plan, [29] and [30] addressed the problem of how to allocate buffers to pre existing buffer blocks. Most recently, 31] proposed to distribute buffer sites throughout the layout. Since buffer insertion is a key technique to reduce interconnect delay and noise and buffers are used extensively in ....

F. Dragan, A. Kahng, I. Mandoiu, S. Muddu, and A. Zelikovsky, "Provably good global buffering using an available buffer block plan," in Proc. Int. Conf. Computer-Aided Design, San Diego, CA, Nov. 2000, pp. 104--109.

No context found.

F.F. Dragan, A.B. Kahng, I.I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably good global buffering using an available buffer block plan", Proc. ICCAD, 2000, pp. 104--109.

No context found.

F. F. Dragan, A. B. Kahng, I. I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably good global buffering using an available buffer block plan", Proc. ICCAD'2000.

No context found.

F. F. Dragan, A. B. Kahng, I. I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably Good Global Buffering Using an Available Buffer Block Plan", Proc. ICCAD, 2000, pp. 104-109.

.... LP with set capacities scaled down by a small factor which guarantees that the rounded solution meets the original capacities with very high probability (see [11] A more practical approach, extending the so called greedy deletion Approximation Algorithms for Separable Packing LPs 11 algorithm in [6] to multiterminal nets, is to repeatedly drop routed paths passing through over used sets until feasibility is achieved. 7 Experimental Results We have implemented four greedy algorithms for the GRBB problem; all four greedy algorithms route nets sequentially. For a given net, the algorithms ....

F.F. Dragan, A.B. Kahng, I.I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably good global buffering using an available buffer block plan", Proc. ICCAD, 2000, pp. 104--109.

....planning problem. In this paper, we address the problem of how to perform buffering of global multiterminal nets given an existing buffer block plan. We give a provably good algorithm based on a recent approach of Garg and K onemann [8] and Fleischer [7] see also Albrecht [1] and Dragan et al. [6]) Our method routes connections using available buffer blocks, such that required upper and lower bounds on buffer intervals as well as wirelength upper bounds per connection are satisfied. In addition, our algorithm allows more than one buffer to be inserted into any given connection and ....

....lower bounds on buffer intervals as well as wirelength upper bounds per connection are satisfied. In addition, our algorithm allows more than one buffer to be inserted into any given connection and observes buffer parity constraints. Most importantly, and unlike previous works on the problem [5, 18, 6], we take into account multiterminal nets. Our algorithm outperforms existing algorithms for the problem [5, 6] which are based on 2 pin decompositions of the nets. The algorithm has been validated on top level layouts extracted from a recent high end microprocessor design. I. INTRODUCTION ....

[Article contains additional citation context not shown here]

F. F. Dragan, A. B. Kahng, I. I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably good global buffering using an available buffer block plan", Proc. ICCAD'2000.

No context found.

F. Dragan, A. Kahng, I. Mandiou, S. Muddu, and A. Zelikovsky. Provably good global buffering using an available buffer block plan. In Proc. Int. Conf. on Computer Aided Design, page 104, 2000.

No context found.

F.F.Dragan, A.B.Kahng, I.Mandoiu, S.Umddu, "Provably Good Global Buffering Using an Available Buffer Block Plan", IEEE/ACM ICCAD, 2000, pp. 104-109

No context found.

F. F. Dragan and A. B. Kahng and I. Mandoiu and S. Muddu and A. Zelikovsky, "Provably Good Global Buffering using an Available Buffer Block Plan", Proceedings IEEE International Conference on ComputerAided Design, pp. 104-109, 2000.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC