J. Lenell, S. Wallace, and N. Bagherzadeh. A 20 MHz CMOS Reorder Buffer for a Superscalar Microcomputer. In 4th Annual NASA VLSI Symposium, November 1992. Home/Search Document Not in Database Summary Related Articles |
This paper is cited in the following contexts:
Design and Implementation of a Scheduling Unit for a Superscalar.. - Dagli (1994) (1 citation) Self-citation (Bagherzadeh) (Correct)
....result tags. CURRENT 8 lookup Searches for most current destination register. Table 4.1: Reorder Buffer Fields 4.2 Basic Cells A detailed description of the various cells used in the design of the Scheduling Unit is included in this Section. The Reorder Buffer is a regularly structured design [10, 17] and all cells used in it are discussed. On the other hand, a lot of custom gates are used in the Instruction Window and an attempt has been made to cover as many of them as possible. The layout plots of some of the cells are also provided. 4.2.1 Reorder Buffer The various fields of the Reorder ....
J. Lenell, S. Wallace, and N. Bagherzadeh. A 20 MHz CMOS Reorder Buffer for a Superscalar Microcomputer. In 4th Annual NASA VLSI Symposium, November 1992.
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