M. N. Velev and R. E. Bryant. Formal Veri cation of Superscalar Microprocessors with Multicycle Functional Units, Exceptions and Branch Predication. In 37th Design Automation Conference (DAC '00), June 2000.  Home/Search Document Not in Database Summary Related Articles Check |
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Strengthening Invariants by Symbolic Consistency Testing - Abu-Haimed, Berezin, Dill (Correct)
....developed in the literature for nding invariants automatically [9, 14, 16, 2, 1, 11] In spite of the sophistication of these techniques, the process of nding invariants is still mostly manual. Symbolic simulation has been used as a tool to reduce the manual e ort in constructing the invariants [14, 15, 17]. Manna and Pnueli [9] showed methods based on bottom up techniques for verifying temporal properties of reactive systems, which are then used to extract assertions implied by the transition relation. These assertions are used to strengthen the invariant. Su et al. 14] presented some heuristics ....
Miroslav N. Velev and Randal E. Bryant. Formal veri cation of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction. In Design Automation Conference (DAC), 2000.
A Symbolic Approach to Predicate Abstraction - Shuvendu Lahiri Randal (2003) (4 citations) Self-citation (Bryant) (Correct)
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M. N. Velev and R. E. Bryant. Formal Veri cation of Superscalar Microprocessors with Multicycle Functional Units, Exceptions and Branch Predication. In 37th Design Automation Conference (DAC '00), June 2000.
A Symbolic Approach to Predicate Abstraction - Lahiri, Bryant, Cook (2003) (4 citations) Self-citation (Bryant) (Correct)
No context found.
M. N. Velev and R. E. Bryant. Formal Veri cation of Superscalar Microprocessors with Multicycle Functional Units, Exceptions and Branch Predication. In 37th Design Automation Conference (DAC '00), June 2000.
Modeling and Verification of Out-of-Order Microprocessors.. - Lahiri, Seshia, Bryant (2002) (2 citations) Self-citation (Bryant) (Correct)
No context found.
M. N. Velev and R. E. Bryant. Formal Veri cation of Superscalar Microprocessors with Multicycle Functional Units, Exceptions and Branch Predication. In 37th Design Automation Conference (DAC '00), June 2000.
Processor Verification Using Efficient Reductions of the.. - Bryant, German, Velev (2001) (10 citations) Self-citation (Velev Bryant) (Correct)
....transitivity constraints, then we have proved that F is universally valid. Goel et al. have shown the constrained Boolean satis ability problem is NP hard, even when F sat is represented as an BDD. We have also studied this problem in the context of pipelined processor veri cation [Bryant and Velev 2000a; 2000b] We have found that we can exploit the sparse structure of the e i;j variables both when using BDDs to perform the veri cation and when using Boolean satis ability checkers. As a result, enforcing transitivity constraints has a relatively small impact on the performance of the decision ....
....of CPU time. By contrast, Burch [1996] veri ed a somewhat simpler dual issue processor only after devising 3 di erent commutative diagrams, providing 28 manual case splits, and using around 30 minutes of CPU time. Our results are far better than any others achieved to date. In more recent work [Velev and Bryant 2000], we ACM Transactions on Computational Logic, Vol. 2, No. 1, January 2001. 40 Randal E. Bryant, et al. have been able to add additional features to our pipeline model, including exception handling, multicycle instructions, and branch prediction. By using appropriate abstractions, most of this ....
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Velev, M. N. and Bryant, R. E. 2000. Formal verication of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction. In 37th Design Automation Conference. 112-117.
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