Kevin Elphinstone, Virtual Memory in a 64-bit Micro-kernel,PhD Thesis, UNSW,1999. ftp://ftp.cse.unsw.edu.au/pub/users/disy/papers/Elphinstone:phd.ps.gz  Home/Search   Document Details and Download   Summary   Related Articles

....R4700 XContext register [23] Support for the R4700 page mask costs only one instruction, as the word containing the page mask is available in a register after the loop terminates. 5. 3 GPT Refill The L4 MIPS micro kernel contains code for many different alternative page table implementations [28]. One of the options in L4 MIPS is for a guarded page table to refill the TLB directly. Figure 5.4 shows the internal node format for this GPT implementation. Even though the guard is typically a few bits in length, 52 bits are reserved as guards can occasionally skip almost all the bits in the ....

....hardware page size to the size of the entire address space. The three L4 primitives can be used to construct arbitrary address space hierarchies. Forexample, Figure 6.1 shows some address spaces constructed using the map operation. 0 s A B C D E Figure 6. 1 Address space composition in L4 [28] As shown in Figure 6.1, L4 even allows pages to be mapped multiple times in one address space, effectively creating aliases, even though no useful purpose is known to exist for this arrangement. The s 0 address space is initialized to contain an identical mapping from virtual to physical ....

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Kevin Elphinstone, Virtual Memory in a 64-bit Micro-kernel,PhD Thesis, UNSW,1999. ftp://ftp.cse.unsw.edu.au/pub/users/disy/papers/Elphinstone:phd.ps.gz

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