Sergei Y. Larin and Thomas M. Conte. Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. In 32nd Int'l Symposium on Microarchitecture, pages 82--92, Haifa, Israel, November 1999. IEEE. Home/Search Document Details and Download
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Memory Expansion Technology (MXT): Software support .. - Abali, Franke.. (2001) (Correct)
....in the memory hierarchy that serves as a paging store. The author introduces this concept to take advantage of the improving speed of processors versus disk, and notes that the growing disparity between these system elements makes compression close to the processor an appealing feature. Reference [9] and the TinyRISC effort use compression to reduce embedded system code size. References [10] and [11] use compression techniques to increase branchprediction accuracy in microprocessors. Reference [12] describes algorithms and data structures for compressedmemory machines. The primary ....
Sergei Y. Larin and Thomas M. Conte, "Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors," Proceedings of the Annual International Symposium on Microarchitecture, 1999, pp. 82--92.
Efficient Execution of Compressed Programs - Lefurgy (2000) (1 citation) (Correct)
....This requires a program to execute more instructions, which reduces performance. For example, Thumb code runs 15 20 slower on systems with ideal instruction memories (32 bit buses and no wait states) ARM95] Custom encodings A somewhat different approach was introduced by Larin and Conte [Larin99]. They assume that the embedded processor can be optimized to a specific program. They use the compiler to generate both the compressed program and a custom programmed logic array to fetch and decompress it. One technique they use is to customize the instruction set for the program by shortening ....
S. Larin and T. Conte, "Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors", Proceedings of the 32nd Annual International Symposium on Microarchitecture, pp. 82-92, November 1999.
Memory Overflow Protection for Embedded Systems using.. - Surupa Biswas Surupa (2004) (Correct)
No context found.
Sergei Y. Larin and Thomas M. Conte. Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. In 32nd Int'l Symposium on Microarchitecture, pages 82--92, Haifa, Israel, November 1999. IEEE.
Trends In Compilable Dsp Architecture - John Glossner Jaime (2000) (Correct)
No context found.
S. Larin and T. Conte, "Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors", Proceedings of the Annual International Symposium on Microarchitecture, 1999, pp 82-92.
LZW-Based Code Compression for VLIW Embedded Systems - Chang Hong Lin (Correct)
No context found.
S. Larin and T. Conte. Compiler-Driven Cached Code Compression Schemes for Embedded ILP Proceesors. Proc. of the Annual Int. Symposium on Microarchitecture, p.82-91, Nov. 1999.
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