C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proc. Fourteenth Annual International Symposium on Computer Architecture, pages 234--243, Pittsburg, PA, June 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....programmability for performance. Sequential consistency was first defined by Lamport [19] in this paper, we use an alternative formulation proposed by Afek et al. 2] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [1, 3, 5, 8, 9, 11, 12, 13, 14, 15, 16, 21, 24]. In most of this work, memory is modeled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy and Wing [17] Sequential consistency and other consistency conditions for ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proc. Fourteenth Annual International Symposium on Computer Architecture, pages 234--243, Pittsburg, PA, June 1987.

....programmability for performance. Sequential consistency was first defined by Lamport [19] in this paper, we use an alternative formulation proposed by Afek et al. 2] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [1, 3, 5, 8, 9, 11, 12, 13, 14, 15, 16, 21, 24]. In most of this work, memory is modeled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy and Wing [17] Sequential consistency and other consistency conditions for ....

C. Scheurich and M.Dubois. Correct memory operation of cache-based multiprocessors. In Proc. Fourteenth Annual International Symposium on Computer Architecture, pages 234--243, Pittsburg, PA, June 1987.

....notion and each one has tried to capture a larger set of sequentially consistent executions. Scheurich and Dubois proposed a sufficient condition for sequential consistency which requires that a processor cannot issue a memory access until its previous write operation has been globally performed [SD87] Brown proposed a protocol for multiprocessor systems which allows invalidation requests to a local cache to be buffered until the shared memory needs to be accessed [Bro90] Afek, Brown and Merritt also proposed a protocol for multiprocessor systems which captured a larger set of executions by ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proceedings of the International Symposium on Computer Architecture, pages 234--243, 1987. 22

....programmability for performance. Sequential consistency was first defined by Lamport [20] in this paper, we use an alternative formulation proposed by Afek et al. 2] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [1, 3, 5, 8, 9, 11, 12, 13, 15, 16, 17, 21, 24]. In most of this work, memory is modeled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy and Wing [18] Sequential consistency and other consistency conditions for ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proc. Fourteenth Annual InternationalSymposium on Computer Architecture, pages 234--243, Pittsburg, PA, June 1987.

....until it receives an acknowledgement for its previous operation. Since pipelining is an important way to decrease effective memory latency, this solution is expensive. The high cost of enforcing sequential consistency has led to extensive exploration of weaker memory consistency models, e.g. [9, 30]. These weaker models are harder to reason about and still impose significant restrictions on pipelining, but make sense given the cost of maintaining sequential consistency in a conventional system. In an isotach system, processes can pipeline memory operations without violating sequential ....

C. Scheurich and M. Dubois, "Correct Memory Operation of Cache-Based Multiprocessors", Proc. 14th ISCA, June 1987, 234-243.

.... always the value given by the latest STORE instruction with the same address [CF78] As noted by Scheurich and Dubois, this definition makes implicit architectural assumptions (specifically as to the atomicity of write operations) that limit its applicability to some multiprocessor architectures [SD87] For systems in which this definition has a natural interpretation, coherence is usually the correctness condition cited. See, e.g. Smi82, KEW 85, YYF85, SS86, Goo87] As we understand the somewhat 3 informal notion, memory systems that are cache coherent are behaviorally ....

....architectural assumptions. The conditions we discuss in Section 3 are stated as restrictions on the allowed sequences of events at an interface between the processors and a shared memory, and do not refer to any of the details of the memory implementation. In a later paper, Scheurich and Dubois [SD87] present a sufficient condition for sequential consistency that is stronger than strong ordering, and show that it is satisfied by many conventional consistency algorithms. As they note, their consistency condition is a restriction of the general definition, and indeed, it excludes our ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In 14th International Symposium on Computer Architecture, pages 234--243, 1987.

....how to preserve the access atomicity of SC with cache coherence protocols, and recent advances in the use of speculative execution permit reordering of loads without destroying the sequentiality of SC. The desire to achieve higher performance has led to various relaxed or weaker memory models [21, 12, 15, 8, 6]. Broadly speaking, weaker memory models weaken either the sequentiality constraint or the atomicity constraint of SC. The weak ordering property allows certain memory accesses to be performed in a different order than the program order unless explicit ordering constraints are specified. The ....

C. Scheurich and M. Dubois. Correct Memory Operation of Cache-based Multiprocessors. In Proceedings of the 14th International Symposium On Computer Architecture, pages 234--243, June 1987.

....memory system to issue a memory operation only when the previous memory operations of that processor have completed. This method maintains ordering of all memory operations as required by SC. Furthermore, a write in SC does not retire from the instruction 21 window until it is globally performed [35]. Unlike the RC model which can retire up to 4 writes a cycle, the SC model can retire only at most 1 write per cycle. To implement hardware prefetching, we issue prefetch requests to the cache as described in Section 2.2. We prefetch requests to the level of cache appropriate for the ....

C. Scheurich and M. Dubois. Correct Memory Operation of Cache-Based Multiprocessors. In Proceedings 14th Annual International Symposium on Computer Architecture, pages 234--243, Pittsburgh, PA, June 1987.

....old data when it tries to read the modified data. This is known as a cache coherency problem. For correct system operation, all reads to a location must return the data most recently written to it. This principal, known as sequential consistency, has been studied carefully for uni processors [26]. For uni processors, a variety of simple solutions can be used. For example, one might require the operating system to ensure that consistency is maintained. Another solution is to use the configuration in Figure 1.2. Unfortunately, this solution reduces the cache hit ratio significantly which in ....

....it is replaced, the new data is also sent to the memory module along with the regular block replacement message. 2.2.4 Lock Bit The Lock Bit is used for making sure that the requests are satisfied in the same order as they are received. This is critical for maintaining sequential consistency [26]. As we mentioned before, the Lock bit for a block is set when an access for the block must wait for acknowledgments from processors to come back to the memory module before the access can be completed. For example, consider the scenario in which processor A issues a write request to block T. If ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In International Symposium on Computer Architecture, pages 234--243, 1987.

....one has tried to capture a larger set of sequentially consistent executions. Scheurich and Dubois proposed a sufficient condition for sequential consistency. The condition prevents a processor from accessing memory until any previous write operation by the processor has been globally performed [SD87]. Brown proposed a protocol for multiprocessor systems which allows invalidation requests to a local cache to be buffered until the shared memory needs to be accessed [Bro90] Afek, Brown and Merritt also proposed a protocol for multiprocessor systems which captured a larger set of executions by ....

Scheurich, C. and Dubois, M. Correct memory operation of cachebased multiprocessors. In Proceedings of the International Symposium on Computer Architecture, pages 234--243, 1987.

....sequentially [Lam79] or processor consistent [GW88] Ordinary memory accesses to different locations are ordered only with respect to synchronization accesses and can be completely reordered between them. The following two definitions are reformulated CHAPTER 5. SCOPE CONSISTENCY 99 after [DSB86, SD87, GLL 90] A complete set of definitions for terms used in consistency models can be found in [AH90] ffl A write is performed with respect to a process P when a read issued to the same address by P will return the value stored by that write (or a subsequent write to the same location) ffl ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proceedings of the 14th Annual Symposium on Computer Architecture, pages 234--243, June 1987.

....caching of the variable, this traffic and contention can be significantly reduced. 1.2 Thesis Organization This thesis is divided into seven chapters. Chapter 2 presents previous work on cache consistency. In Chapter 3, the conditions for sequential consistency proposed by Scheurich et al. [Scheurich 1987; Dubois 1988; Scheurich 1989] are reviewed and discussed. Chapter 4 presents the proposed cache consistency scheme in the context of a generic system and shows, using the conditions discussed in Chapter 3, that the scheme enforces sequential consistency. How this scheme might be applied to an ....

....it is sufficient to demonstrate that the event ordering rules are not violated. To date, however, there have been no practical applications of these rules for cache based systems with general interconnects. The approach presented in a collection of papers by Dubois, Scheurich and Briggs [Scheurich 1987; Dubois 1988; Scheurich 1989] uses the same idea as Collier s write synchronization rule. A set of conditions for consistency is proposed that ensures that every processor will observe writes in the same order. These conditions are applicable to a wide class of shared memory architectures. In ....

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Scheurich, C. and Dubois, M. (1987). Correct Memory Operation of Cache-based Multiprocessors. Proc. of the 14th Annual International Symposium on Computer Architecture, pages 234--243.

.... if it is equivalent to a serial execution in which the operations issued by each process are executed in the order specified by the program [Lam79] Sequential consistency, and thus memory coherence, can be ensured in systems with caches by prohibiting pipelining of accesses to shared variables [ScD87]. Since pipelining is an important technique for reducing effective memory latency in multiprocessors, researchers have proposed enforcing a weaker form of sequential consistency allowing some pipelining by relaxing ordering constraints between synchronization points [AdH90,DSB86] With the ....

C. Scheurich and M. Dubois, Correct Memory Operation of Cache-Based Multiprocessors, Proc. 14th Int. Symp. Computer Architecture, June 1987, 234-243. 43

....ongoing project of automatically verifying the SCI protocol. They have discovered several errors in the C code which defines that protocol. An overview of the SCI protocol and related projects can be found in [12] There is a vast amount of work done on other cache coherence algorithms, see, e.g. [1, 34, 35, 16] to name just a few of them. The algorithm proposed by Afek, Brown, and Merritt in [1] explores a formalization of Lamport s notion of sequential consistency [25] Whereas cache coherence ensures that processors have a consistent view of the cache, sequential consistency addresses the question in ....

C. Schreurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In 14th International Symposium on Computer Architecture, pages 234--243, Los Angeles, 1987. IEEE Computer Society.

....ongoing project of automatically verifying the SCI protocol. They have discovered several errors in the C code which defines that protocol. An overview of the SCI protocol and related projects can be found in [14] There is a vast amount of work done on other cache coherence algorithms, see, e.g. [1, 36, 37, 18] to name just a few of them. The algorithm proposed by Afek, Brown, and Merritt in [1] explores a formalization of Lamport s notion of sequential consistency [27] Whereas cache coherence ensures that processors have a consistent view of the cache, sequential consistency addresses the question of ....

C. Schreurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In 14th International Symposium on Computer Architecture, pages 234--243, Los Angeles, 1987. IEEE Computer Society.

....Programs In parallel and distributed programs where processes share data, access to data is controlled by synchronization operations. When programs use sufficient synchronization to control access to shared data, consistency maintenance can be limited to the synchronization points [52]. Adve and Hill [2] formalized this and introduced the notion of data race free programs. In these programs, conflicting accesses to a shared location by different processors (two accesses to a memory location conflict when they are not both reads) are always separated by one or more ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proceedings of the 14th Annual Symposium on Computer Architecture, June 1987.

....can be weakened for systems that satisfy only the PLpc memory model. To provide SC executions, it is sufficient if (i) accesses of a single processor are executed one at a time in program order, and (ii) a write is made visible to all processors simultaneously (referred to as atomicity) [16]. If (i) is satisfied, it follows that a weaker notion of the atomicity condition in (ii) suffices: it is sufficient if a write becomes visible simultaneously to all processors other than the one that issued the write. In the following, we use atomic to refer to this weaker notion. The ....

C. Scheurich and M. Dubois, Correct Memory Operation of Cache-Based Multiprocessors, Proc. Fourteenth Annual Intl. Symp. on Computer Architecture, Pittsburgh, PA, June 1987, 234-243.

....programmability for performance. Sequential consistency was first defined by Lamport [26] in this paper, we use an alternative formulation proposed by Afek et al. 4] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [2, 3, 5, 11, 12, 15, 17, 18, 19, 20, 21, 28, 33]. A valuable survey of these ideas is given by Adve and Gharachorloo [1] In most of previous work, memory is modelled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy ....

C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proc. Fourteenth Annual International Symposium on Computer Architecture, pages 234--243, Pittsburg, PA, June 1987.

....suffices to say that many models make use of an mechanism called a weak write. A weak write allows a processor to continue execution after starting an invalidation and before all stale copies of the data have been invalidated. This is not allowed when the hardware implements sequential consistency [ScDu87]. The weaker memory models usually require a mechanism to test or signal when all copies are invalidated. We mention weak writes because this mechanism should be incorporated into a cache coherence protocol. An efficient cache coherence protocol for thousands of processors must be scalable. Our ....

....accesses in program order) because the protocol defines a partial ordering on all memory accesses such that there exists a global ordering that is consistent with program order. Another proof sketch is that our combining fetch and add meets the sufficient conditions defined by Scheurich and Dubois [ScDu87] 29 . For hardware simplicity, we expect combining fetch and add to be defined on the first 8 byte integer in a line. However, the mechanism can be extended to combine fetch and adds on ########################### 28 It is sufficient to wait for valid data with insertions and nonpurging ....

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Christoph Scheurich and Michel Dubois, "Correct Memory Operation of CacheBased Multiprocessors," Proceedings of the Fourteenth Annual International Symposium on Computer Architecture, June 1987, 234-243.

....executions, as allowed by Theorem 1. 4. 1 Executing Memory Operations Out of Program Order Typical implementations ensure the program order requirement of sequential consistency by prohibitinga process from executing a memory operation until its preceding operation (by program order) is complete [48]. A read completes when it returns a value, while a write completes when its value has become visible to all other processors [48] However, out of order execution may be desirable in many situations; e.g. to exploit a write buffer that lets a read bypass a preceding write of its processor, or ....

.... order requirement of sequential consistency by prohibitinga process from executing a memory operation until its preceding operation (by program order) is complete [48] A read completes when it returns a value, while a write completes when its value has become visible to all other processors [48]. However, out of order execution may be desirable in many situations; e.g. to exploit a write buffer that lets a read bypass a preceding write of its processor, or to exploit a lockup free cache that services hits or misses while a preceding miss of its processor is incomplete, or to fully ....

[Article contains additional citation context not shown here]

C. Scheurich and M. Dubois. Correct Memory Operation of Cache-Based Multiprocessors. In Proc. 14th Ann. Intl. Symp. on Computer Architecture, pages 234--243, Pittsburgh, PA, June 1987.

....the copy of the block to any processor experiencing a miss. In a write update protocol data consistency is maintained by updating all remote data copies instead of invalidating them. Cache protocols must enforce that all processors observe all stores to the same memory location in the same order [81]. Memory accesses to the same memory location must be performed in program order. As a result, when all processors cease to write and all stores in propagation are performed, all data copies of the same memory location must be identical. This is the so called general coherency property [83] which ....

....and one liveness property ( good things will occur in the future ) to verify. They are defined as follows: Data consistency. In a cache coherent system, data consistency among multiple data copies is typically enforced by allowing one and only one store in progress at any time for each block [81]. Concurrent accesses to the same block can be executed on different data copies but must appear to have executed atomically in some sequential order. The cache protocol must always return the latest value on each load. Incomplete Protocol Specification. When possible state transitions have ....

[Article contains additional citation context not shown here]

Scheurich, C. and Dubois, M., "Correct Memory Operation of Cache-Based Multiprocessors ", Proc. of the 14th Int'l Symposium on Computer Architecture, June, 1987, pp.234-243.

....of deadlocks or livelocks are three important requirements for the intrinsic correctness of a coherence protocol. In systems where writes are not atomic, data consistency between multiple data copies is typically enforced by allowing one and only one update in progress at any time for each block [14]. As a result, concurrent accesses can be executed on different data copies but will appear to have executed atomically in some sequential order. The cache protocol must always return the latest value in this order on each load. An unspecified message reception occurs when some entity in the ....

....consistency of its values might be preserved in a protocol, without respecting the global ordering of accesses imposed by the memory consistency model. For example, strongly ordered memory systems supporting sequential consistency mandate that all accesses be globally performed in program order [14]. This property of the system must be verified. This aspect of the verification of protocol correctness is very complex and is still an open question. 4.3. Protocol Implementation Errors. These errors stem from the semantic gap between the architectural model used in the elimination of ....

Scheurich, C. and Dubois, M., "Correct Memory Operation of Cache-Based Multiprocessors", Proc. of the 14th Int'l Symposium on Computer Architecture, June, 1987, pp.234-243.

....TxOS solves a similar race occurring when p 1 first requests an exclusive copy, while p 2 wants a shared copy (see Figure 2. c) Traditionally, while a coherence transaction is in progress, the directory entry must be locked to maintain a critical (semi critical) section on each memory block [22, 26, 28]. The scenarios of Figure 2 violate this requirement: the directory entry is unlocked after sending the response (such as the data block) to the requester. This optimization does not compromise correctness in systems with FIFO networks. In systems with non FIFO networks the additional transient ....

....data block may be costly. FIGURE 4. A Ghost Message. 4 Correctness Issues of the Protocol 4. 1 Data Consistency In systems where writes are not atomic, data consistency between multiple data copies is typically enforced by allowing one and only one update in progress at any time for each block [26]. As a result, concurrent accesses can be executed on different data copies but will appear to have executed atomically in some sequential order. The cache protocol must always return the latest value on each load. We formulate this condition within the framework of the reachability expansion as ....

Scheurich, C. and Dubois, M., "Correct Memory Operation of Cache-Based Multiprocessors ", Proc. of the 14th Int'l Symposium on Computer Architecture, June, 1987, pp.234-243.

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C. Scheurich and M. Dubois. Correct memory operation of cache-based multiprocessors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 234-243, June 1987.

No context found.

Christoph Scheurich and Michel Dubois. Correct Memory Operation of Cache-based Multiprocessors. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 234--243, May 1987.

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