W. C. Brantley, K. P. McAuliffe and J. Weiss, RP3 Process-Memory Element, International Conference on Parallel Processing, August 1985, 772-781. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Weak Ordering - A New Definition And Some Implications - Adve, Hill (1989) (7 citations) (Correct)
....one single bus. Memory is divided into distinct modules and each module is connected to all processors through exactly one bus. The RP3 system built at IBM, in cooperation with the Ultracomputer project from NYU, is a cache based system, where processor memory communication is via an Omega network [BMW85,GGK83, PBG85]. However, in this system, the management of cache coherency for shared, writable variables is entrusted to the software. Thus from the viewpoint of the hardware, the RP3 is similar to the system studied by Lamport in [Lam79] The second condition given by Lamport is met in the RP3, by requiring a ....
W. C. Brantley, K. P. McAuliffe and J. Weiss, RP3 Process-Memory Element, International Conference on Parallel Processing, August 1985, 772-781.
Implementing Sequential Consistency In Cache-Based Systems - Adve, Hill (1990) (22 citations) (Correct)
.... We first show that strong ordering, proposed by Dubois, Scheurich and Briggs [DSB86] is not equivalent to sequential consistency (Section 2) Next we introduce the second, common approach for implementing sequential consistency that requires processors to perform memory references one at a time [BMW85, RuS84, ScD87], and illustrate with sufficient conditions and an implementation proposal that this one at a time approach is not necessary in practice (Section 3) 2. Strong Ordering Strong ordering was defined by Dubois, Scheurich and Briggs in [DSB86] as follows: In a multiprocessor system, storage accesses ....
.... are connected to memory through a common bus, most of the cache coherence protocols proposed in the literature satisfy this condition [ArB86, RuS84] The RP3 is a cache based system that consists of a general interconnection network but does not support the caching of shared variables in hardware [BMW85]. Sequential consistency is maintained by stalling on every request to memory until an acknowledgement is obtained, again satisfying the one at a time condition. For cache based systems with general interconnects that allow shared variables to be cached, a cachecoherence protocol is not ....
W. C. Brantley, K. P. McAuliffe and J. Weiss, RP3 Process-Memory Element, International Conference on Parallel Processing, August 1985, 772-781.
Designing Memory Consistency Models For Shared-Memory.. - Adve (1993) (30 citations) (Correct)
....that detect non local shared memory accesses in high level code, and convert them into appropriate messages for the underlying message passing machine [HKT92] Several systems employ a combination of hardware and software techniques. For example, in systems using software based cache coherence [BMW85, ChV88, PBG85], hardware provides a globally addressable memory, but the compiler is responsible for ensuring that shared data in a cache is up to date when required by its processor. The Alewife system [ALK90] and the Cooperative Shared Memory scheme [HLR92] manage cacheable shared data in hardware for the ....
....protocols for bus based systems. They formally prove the protocols obey their correctness criteria mentioned in Section 2.1. 2; if we assume they implicitly considered processors that execute operations in program order, the protocols guarantee sequential consistency [RuS84] The RP3 system [BMW85, PBG85] is a cache based system, where processor memory communication is via an Omega network, but the management of cache coherence for shared writable variables is entrusted to the software. For sequential consistency, a process must wait for an acknowledgement from memory for its preceding miss on a ....
[Article contains additional citation context not shown here]
W. C. BRANTLEY, K. P. MCAULIFFE and J. WEISS, RP3 Process-Memory Element, International Conference on Parallel Processing, August 1985, 772-781.
Comparison of Hardware and Software Cache Coherence Schemes - Adve, Adve, Hill, Vernon (1991) (37 citations) (Correct)
....medium to maintain coherence. Hardware directory protocols [ASH88] can be used with a large number of processors, but they are complex to design and implement. An alternative to hardware cache coherence is the use of software techniques to keep caches coherent, as in Cedar [KDL86] and RP3 [BMW85]. Software cache coherence is attractive because the overhead of detecting stale data is transferred from runtime to compile time, and the design complexity is transferred from hardware to software. However, software schemes may perform poorly because compile time analysis may need to be ....
W. C. BRANTLEY, K. P. MCAULIFFE and J. WEISS, RP3 Process-Memory Element, Intl. Conf. on Parallel Processing, August 1985, 772-781.
Weak Ordering - A New Definition - Adve (1990) (196 citations) (Correct)
....For single bus cache based systems, a number of cache coherence protocols have been proposed in the literature [ArB86] Most ensure sequential consistency. In particular, Rudolph and Segall have developed two protocols, which they formally prove guarantee sequential consistency [RuS84] The RP3 [BMW85, PBG85] is a cache based system, where processor memory communication is via an Omega network, but the management of cache coherence for shared writable variables is entrusted to the software. Sequential consistency is ensured by requiring a process to wait for an acknowledgement from memory for its ....
W. C. BRANTLEY, K. P. MCAULIFFE and J. WEISS, RP3 Process-Memory Element, International Conference on Parallel Processing, August 1985, 772-781.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC