M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", IEEE Conference on Computer-Aided Design, pp. 446-451, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....1403 1885 1084 1403 1885 1321 1503 1900 improvement ( 0.0 19.3 10.5 2.1 19.3 10.9 13.3 16.0 12.4 Table 4. Experimental results of adaptive scheduling for real life examples without algorithm selection. We have constructed 4 different sets of 12 tasks from the 16 real life tasks described in [16]. The tasks are the following: two GE controllers, two Honda controllers, a wavelet filter, four audio filters, a 8 Theta 8 discrete cosine transform, an NEC digital to analog converter, two components of modems, a LMS audio formatter, an echo canceler, and a linear controller for automotive ....

M. Potkonjak, W. Wolf: "Cost Optimization in ASIC Implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", International Conference on Computer-Aided Design, pp. 446451, 1995.

....non standard video algorithms. One approach to a verifiable benchmark set is to enumerate all variants of a system including the expected changes. In [44] such a solution was proposed for ASIP design, derived from a very similar solution for systems with concurrent processes but without variants [45]. Different tasks with timing requirements were serialized into a single large sequential process which was, then, synthesized such that all timing requirements of all tasks were met. Notably, synthesis turned out to be very sensitive to the order in which the variants (here: the different ....

Potkonjak, M. and Wolf, W. (1995) Cost Optimization in ASIC Implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques. Proc. ICCAD 95, San Jose, 446 - 451.

....and commercial developers [Bol94] Shortened design cycles, due to market pressure, have encouraged the use of predesigned processor cores. At the same time, market pressure to reduce system cost for consumer products has spurred the development of system level synthesis techniques [Wol94] [Pot95], Chi96] Lin96] Sub96] As embedded applications have become more sophisticated and commercially relevant, hardware software codesign and techniques for system level synthesis have also become increasingly important [Gup93] Gaj94] Ism94] Hen95] Lee96] Chu96] The increased interest ....

M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", ICCAD95, San Jose, CA, pp. 446-451, 1995.

.... effective when applied early in the design process at the algorithmic and architectural level, majority of power minimization techniques have been proposed for logic synthesis and physical design [16] Potkonjak and Rabaey presented a CAD system level synthesis approach which targets low power [15]. However, the scope of this effort is restricted to a single task application specific system. Several system level optimizations have been proposed in [14] Hard real time scheduling efforts have been an important topic for research since early computing days. The initial research on scheduling ....

M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", ICCAD95, pp. 446-451, 1995.

....using the Hyper estimation tools which calculate the maximum cutset of the dataflow graph [Rab91 ] as measured by the ratio of the estimated number of registers in the initial designs. Note that the preference measures based on different observations may be contradictory. In our previous attempt [Pot95] we used a rank based function of a similar set of observation to guide the search. However, both intuition and experimentation indicates that it is sometimes important to consider all four measure simultaneously in a bal anced way. We accomplish this goal by forming a weighted average of the ....

M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", IEEE Conference on Computer-Aided Design, pp. 446-451, 1995.

....adaptive schedule from the nonadaptiveone. The CPU times reported are the running times on SUN Sparc 4. The adaptivescheduling approachhas achieved the average 13.1 improvement from the nonadaptiveapproach. We have constructed 4 different sets of 12 tasks from the 16 real life tasks described in [10]. The tasks are the following: twoGEcontrollers, two Honda controllers, a wavelet filter, four audio filters, a 8 Theta 8 discrete cosine transform, an NEC digital to analog converter, two components of modems, a LMS audio formatter, an echo canceller, and a linear contrller for automotive motion ....

M. Potkonjak, W. Wolf: "Cost Optimization in ASIC Implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", International Conference on Computer-Aided Design, pp. 446-451, 1995.

....both research and commercial developers. Due to market pressure, shortened design cycles have encouraged the use of predesigned processor cores. At the same time, market pressure to reduce system cost for consumer products has spurred the development of system level synthesis techniques [5] 10] [28]. The developed system synthesis techniques have been focused on task scheduling and resource allocation algorithms [23] and interface design and verification [5] Design for composability and ease of core synchronization has been addressed at the system and communication level [6] As embedded ....

M. Potkonjak and W. H. Wolf, "Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques," in Proc. Int. Conf. Computer-Aided Design, 1995, pp. 446--451.

....multiprocessor platform. Both traditional behavioral synthesis and emerging system synthesis, however, have been focused on synthesis of single task applications [11] 27] 49] Recently, Potkonjak and Wolf developed an algorithm for the synthesis of multitask applications at the behavioral level [34]. A few research groups addressed synthesis of hard real time systems [35] 52] but usually under restricted design scenarios. This research project has been motivated for developing an approach to system level synthesis of hard real time multitask multiprocessor systems. In fact, a number of ....

....(2=5) 5=8) Theta (3=10) 0:67. The utilization factor provides a good measure whether a feasible schedule can be found or not. It is also important to note that when the utilization is too high, which means that there is high probability of not being able to generate a feasible schedule [34], we need to know what portion of the task sets can be scheduled on the allocated processors to proceed with the search. We perform a relaxed scheduling on the partitioned task set using our force directed delay based EDF which will be described in Section 8. When no feasible schedule can be ....

[Article contains additional citation context not shown here]

M. Potkonjak and W. H. Wolf. Cost optimization in ASIC implementation of periodic hard real-time systems using behavioral synthesis techniques. In ICCAD95, pages 446--451. International Conference on ComputerAided Design, 1995.

....three lines: application specific system synthesis, processor and memory hierarchy design and energy efficiency evaluation, and cache line coloring techniques. The market driven need for application specific system cost reduction has spurred the development of system level synthesis techniques [Wol94, Pot95]. As embedded applications have become more sophisticated and commercially relevant, hardware software codesign and techniques for system level syn thesis have also become increasingly important [Gup93, Gaj94] The importance of low power design has resulted in adequate treatment of these ....

M. Potkonjak, W.H. Wolf. Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques, ICCAD, pp. 446-451, 1995.

....both research and commercial developers [Bol94] Shortened design cycles, due to market pressure, have encouraged the use of predesigned processor cores. At the same time, market pressure to reduce system cost for consumer products has spurred the development of system level synthesis techniques [Pot95, Chi96, Sub96]. As embedded applications have become more sophisticated and commercially relevant, system level synthesis has also become increasingly important [Gup93, Gaj94, Hen95, Lee96] The increased interest in embedded system design with reusable core components has encouraged the development of high ....

M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", ICCAD, pp. 446-451, 1995.

....such requests. Both traditional behavioral synthesis and emerging system synthesis have been focused on synthesis of single task applications [Gaj92, Wal91, McF90] It is fairly recent development that a technique for synthesis of multi task applications at the behavioral level has been proposed [Pot95]. Also only a few research groups addressed synthesis of hard real time systems [Pra94, Yen95] usually under restricted designed scenarios. Our goal of the research presented in this paper is to develop a modular, flexible, and reusable synthesis tools for system level synthesis of multi task ....

....and available time. P1 P2 P1 estimated cost P1 estimated cost t1 2 5 3 5 (2 5) 3 (3 5) 2 t2 3 5 2 5 (3 5) 2 (2 5) 3 t3 5 8 3 8 (5 8) 3 (3 8) 5 Table 3: Probability and execution time table for relaxed assignment and scheduling 10 of 23 high probability of not having a feasible schedule [Pot95], we need to know what portion of the task sets can be scheduled on the allocated processors to proceed with the search. To do that, we perform a relaxed scheduling on the partitioned task set using our force directed EDF which will be described in the section 7. In the process, if we encounter a ....

[Article contains additional citation context not shown here]

M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", ICCAD95 International Conference on Computer-Aided Design, pp. 446-451, 1995.

....1059 1403 1885 1084 1403 1885 1321 1503 1900 improvement ( 0.0 19.3 10.5 2.1 19.3 10.9 13.3 16.0 12.4 Table 4: Experimental results of adaptive scheduling for real life examples without algorithm selection. We have constructed 4 different sets of 12 tasks from the 16 real life tasks described in [15]. For each task, we have used the number of operations and the area of implementation as the running time and the memory requirement, respectively. The context switching times are approximated such that they are proportional to memory requirement, the switching between similar tasks costs little ....

M. Potkonjak, W. Wolf: "Cost Optimization in ASIC Implementation of Periodic HardReal Time Systems using Behavioral Synthesis Techniques", International Conference on Computer-Aided Design, pp. 446-451, 1995.

.... most effective when applied early in the design process at the algorithmic and architectural level, majority of power minimization techniques have been proposed for logic synthesis and physical design [9] Potkonjak and Rabaey presented a CAD system level synthesis approach which targets low power [8]. Hard real time scheduling efforts have been an important topic for research since early computing days. A survey of the key results in hard real time scheduling and assignment is given in [10] 3 Preliminaries We assume that all tasks are periodic and defined as one way infinite streams of ....

M. Potkonjak and W.H. Wolf. Cost optimization in asic implementation of periodic hard-real time systems using behavioral synthesis techniques. In ICCAD, pages 446--451, 1995.

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