F. Dartu and L. T. Pileggi. TETA: Transistor-Level Engine for Timing Analysis. Proceedings of the Design Automation Conference, pages 595--598, June 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....cases, we can refine the Elmore estimate by selecting one assignment from each Elmore class and simulate it in a high accuracy SPICE like simulator. In doing so, we are essentially using the symbolic computation as a pre processor for selecting input assignments. We are utilizing TETA[1, 11], a fast, callable circuit simulator with accuracy comparable to SPICE. By using a successive chord integration method and a table a b b D 1.2 5.7 Inf. d c c c Figure 3.13: MTBDD Paths lookup model for I ds currents, TETA can re use expensive LU factorization results across multiple ....

F. Dartu and L. T. Pileggi. TETA: Transistor-Level Engine for Timing Analysis. Proceedings of the Design Automation Conference, pages 595--598, June 1998.

....such algorithms are unable to preserve passivity and stability. Without preserving the passive nature of the interconnect, subsequent analyses with nonlinear devices can cause instability, as discussed later in this paper. The proposed framework is embedded with a waveform evaluation engine TETA[6][7] which was developed for use in timing analysis. TETA provides efficient rantime accuracy tradeoffs in handling nonlinear devices and offers several benefits for statistical analyses. Unlike macromodeling approaches, TETA employs interconnect friendly linear centric device models without ....

....circuit simulators. The simulation of linear models with nonlinear devices using a general Newton based linearization approach strongly needs a passive linear model [7] 3.2. TETA: Linear Centric Simulation Engine TETA is a fast transistor level timing simulation engine with almost SPICE accuracy[6] [7] 9] Unlike other timing simulators, TETA uses Successive Chords (SC) technique to solve the associated nonlinear system of equations creating fixed affine linearizations for nonlinear circuit elements. The SC method and splitting the linear and nonlinear portions of the circuit, create ....

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Dartu, F. and L. Pileggi, "TETA: Transistor-level engine for timing analysis", Proc. IEEE/ACMDAC, Jun 1998.

....selecting a sensitizing input assignment from each delay class and recomputing the delay using a SPICE like circuit simulator. In this way, the symbolic Elmore delay becomes a heuristic pre processing routine for selecting input assignments. The circuit simulator we have been working with is TETA [1, 7], from Carnegie Mellon. It is essentially a fast, callable circuit simulator with accuracy comparable to SPICE. By using a successive chord integration method and a table lookup model for DE F currents, TETA can re use expensive LU factorization results across multiple timesteps and input ....

F. Dartu and L. T. Pileggi. TETA: Transistor-Level Engine for Timing Analysis. Proceedings of the Design Automation Conference, pages 595--598, June 1998.

....selecting a sensitizing input assignment from each delay class and recomputing the delay using a SPICE like circuit simulator. In this way, the symbolic Elmore delay becomes a heuristic pre processing routine for selecting input assignments. The circuit simulator we have been working with is TETA [1, 7], from Carnegie Mellon. It is essentially a fast, callable circuit simulator with accuracy comparable to SPICE. By using a successive chord integration method and a table lookup model for DE F currents, TETA can re use expensive LU factorization results across multiple timesteps and input ....

E. Acar and L. T. Pileggi. TETA: Transistor-Level Engine for Timing Analysis. CMU Internal Report, 2000.

....source. The successive chord iterative method is then used to solve the harmonic balance nonlinear system of equations that are formulated by these linear centric models. The successive chord iterative method has been recently applied for time domain transistor level timing analysis (TETA) in [3][4] 5] 6] For the simplicity of terminology, we refer to our new harmonic balance approach as SC balance.Incontrastto Newton Raphson based method and the relaxation variants, for which a nonlinear circuit is linearized at every iteration step, the nonlinear circuit is linearized once, prior to ....

....(8) is used for all iterations in our linearcentric approach such that there is no need to evaluate any derivative. Only the currents (charges) themselves need to be evaluated. Hence, our approach allows the use of lookup table based device models, in which sensitivities are not directly required [3][4] 5] 6] In the detailed device model implemented in our prototyped simulator, N R method needs to evaluate 17 derivatives for a MOSFET and its nonlinear capacitive parasitics at each sampled time point. Then, 17 DFTs are required to transform these 17 derivatives into frequency domain. Saving ....

F. Dartu and L. Pileggi, "TETA: transistor-level engine for timing analysis," Proc. of 35 th DAC, 1998.

....methods as much as possible. But as indicated above, the simplicity of the ftd algorithm can lead to better runtime efficiency because it is more easily optimized for a wide variety of computer platforms. In the second example, ftd was used with TETA(Transistor level Engine for Timing Analysis)[6] to simulate a simple coupled RLC line problem with SPICE like nonlinear drivers. The loads at the far ends of the lumped transmission model are linear capacitors, as shown in Fig.3. The interconnect is a six port with six identical nonlinear drivers. The reduced order model of the two port is ....

F. Dartu and L.T. Pileggi, "TETA: Transistor-Level Engine for Timing Analysis", IEEE/ACM Proc. DAC, Jun. 1998.

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F. Dartu and L. T. Pileggi. TETA: Transistor-Level Engine for Timing Analysis. Proceedings of the Design Automation Conference, pages 595--598, June 1998.

No context found.

E. Acar and L. T. Pileggi. TETA: Transistor-Level Engine for Timing Analysis. CMU Internal Report, 2000.

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F. Dartu et al., "TETA: transistor-level engine for timing analysis," Proceedings of the Design Automation Conference, pp. 595-8, June 1998.

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F. Dartu and L. Pileggi, "TETA: Transistor-level engine for timing analysis," in Proceeding of the 35th Design Automation Conference, 1998, pp. 595--598.

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