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P.J. Black et al., "A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder," IEEE J. Solid-State Circuits, Vol. 32, No. 6, June 1997, pp. 797-805.

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High Speed Electrical Signalling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998)   (3 citations)  (Correct)

....Once the receiver has to deal with multi level signals, one can further improve the performance of the link by allowing symbols to overlap, and accounting for it in the detector. When the input consists of the sum of previous bits, a sequence detector (convolutional coders or Viterbi detectors [48]) is used to determine the transmitted bits. Instead of deciding the transmitted values on a bit Cf bw 1 SN ( log = HOROWITZ et al. Electrical Signalling. 22 by bit basis, these detectors receive an entire bit sequence prior to making a decision. Thus they are able to use the signal ....

Black, P.J. et al. "A 1-Gb/s, four-state, sliding block Viterbi decoder" IEEE Journal of Solid-State Circuits, June 1997. vol.32, no.6, p. 797-805


.3-m CMOS 8-Gb/s 4-PAM Serial Link Transceiver - Ramin Farjad-Rad Student   (Correct)

....is the design and implementation of the high speed link receiver. Details of the transmitter architecture are discussed in [5] II. SYSTEM ARCHITECTURE Implementing truly optimal detection methods (in the information theoretical sense) for multi Gb s rates demands high complexity and large area [3]. Instead, square pulses, which can be generated and detected with modest complexity, are Manuscript received August 1, 1999; revised November 29. 1999. This work was supported by the Powell Foundation. The authors are with the Center for Integrated Systems, Stanford University, Stanford, CA ....

P. J. Black and T. Meng, "A 1-Gb/s, four-state, sliding block viterbi decoder, " IEEE J. Solid-State Circuits, vol. 32, pp. 797--805, June 1994.


High-Speed Electrical Signaling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998)   (13 citations)  (Correct)

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P.J. Black et al., "A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder," IEEE J. Solid-State Circuits, Vol. 32, No. 6, June 1997, pp. 797-805.

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