S. Khatri et al. "A novel VLSI layout fabric for deep sub-micron applications," Proc. of DAC 1999, pp. 491-496, June 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....completely eliminate the crosstalk problem and the protection techniques [ 11 ] are still needed to completely eliminate the cross talk. Also, we do not consider the crosstalk noise at the input (output) lines because the input (output) lines can be separated by ground or power lines as in [4][6]. We have performed experiments on a large set of MCNC benchmark circuits. The results show that after re ordering, 86 of product lines become crosstalk immune and need not be considered for crosstalk prevention. 2. Crosstalk alleviation in dynamic PLA In this section, we discuss two techniques ....

S. P. Khatri, A. Mehrotra, R. K. Brayton, and A. Sangiovanni-Vincentelli, "A Novel VLSI Layout Fabric for Deep Sub-Micron Applications", Proc. DAC, pp. 491-496, 1999.

....as a side metrics. When considering buses (or any global wire) the most intuitive solution consists of spacing the wires, which tends to reduce crosstalk at the source. Another approach consists of shielding the wires by inserting alternating ### and ground lines between existing wires [6]. Although the latter seems to be promising, the former is more well accepted because it does not require additional capabilities from existing place and route tools, and will be used as the reference solution for our work. The point addressed in this paper is that the conventional, uniform ....

S.P. Khatri, A. Mehrotra, R.K. Brayton, R.H.J.M. Otten, A. Sangiovanni-Vincentelli "A novel VLSI layout fabric for deep submicron applications" 36th DAC, pp. 491-496, Jun. 1999.

....a glitch could cause erroneous switching and logic failures. In order to solve this cross talk noise problem, we tested the most popular cross talk noise reduction techniques against this example. 2. 1 Shielding Technique Shielding is one of the most successful existing noise reduction techniques [4,5]. The technique, as shown in Figure 2, interdigitates signal lines with Vdd or Vss alternatively.Figure 3 shows that even when we use the shielding technique, avoltage glitch of 0.54V will still appear. Figure 4 shows that when the inductance is not modeled, the shielding technique appears to ....

S. Khatri, A. Mehrotra, R. Brayton, A. SangiovanniVincentelli, and R. Otten," A Novel VLSI Layout Fabric for Deep Sub-Micron Applications," ACM/IEEE DAC 1999.

....and the physical placement of these point like blocks becomes absolutely critical to the overall wire planning quality, which represents a daunting physical design problem. Another work proposed an interconnect fabric based on a ground signal ground wire grid to make wire loads more predictable [37]. However, this technique results in significant area penalty. Apart from the increasing signal transmission delays of global signals relative to the clock period and gate delay, there are signal integrity concerns arising from electromagnetic interference such as interconnect crosstalk, ....

S. P. Khatri, A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli, and R. H. J. M. Otten, "A novel VLSI layout fabric for deep sub-micron applications," in Proc. 36th ACM Design Automation Conf., 1999, pp. 491--496.

....two consecutive grounded shield wires) On the other hand, shield insertion can compromise signal propagation, since wires must be thinner and more closely spaced in order to maintain a prescribed number of signal wires per unit of channel height. The extreme case of shielding is described in [22] where every signal wire has a ground and V dd wire as its two nearest neighbors. In this study, we look to minimize the cost of a design while achieving good performance. The width of the shield wires (W shield ) and signal wires (W sig ) the spacing between signal wires (S sig ) and the ....

S. P. Khatri, A. Mehrotra, R. K. Brayton, A. SangiovanniVincentelli, and R.H.J.M. Otten, "A novel VLSI layout fabric for deep submicron applications," Proc. of DAC, pp. 491-496, 1999.

.... methodology to make certain issues ignorable. Examples include (i) rules for repeater insertion, slew time control, and layer assignment to solve sizing and signal integrity issues [19, 9] ii) rules for grounded shielding to improve inductance estimation [9] or (iii) noise free fabrics [21]. These avenues to design convergence, while reasonable and viable, share several technical challenges. 1) RTL partitioning must create blocks that can be placed and budgeted well, and also must recognize and diagnose a physically challenged RTL. 2) Block packing mindsets must give way to ....

....productivity and available transistors: if designer resources are not expanded to fill the gap, then large chips must contain more free (memory) transistors. 3 However, this does not create high value designs. 2) Making the back end implementation easier (e.g. with noise free circuit fabrics [21]) or enabling easier block reuse in SOC (e.g. via communication based design ( TCP IP on chip ) 25] improves productivity but harms density and performance. Again, high value designs are not possible. Observation 4: There is no known solution to the implementation gap that does not compromise ....

S. P. Khatri, A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli and R. H. J. M. Otten, "A Novel VLSI Layout Fabric for Deep Sub-Micron Applications", in Proc. ACM/IEEE Design Automation Conf., pp. 491-496, 1999.

....to maximize interconnect performance at the cost of increased routing area [19] By inserting ground and V dd shield wires, current return paths can be clearly defined and loop inductance can be reduced compared to cases without explicit shielding. The extreme case of shielding is described in [20] where every signal wire has a ground and V dd wire as its two nearest neighbors. In this study, we seek to minimize the cost of a design while achieving good performance. The width of the shield wires (W shield ) and signal wires (W sig ) the spacing between signal wires (S sig ) and the ....

....which corresponds to the optimal pitch, not just the optimal line width. Nominal and pessimistic switch factors may have such an inflection point, but they do not fall 4 Fringing capacitance is taken as the difference between the total line capacitance and the parallel plate capacitance from [20]. in the design space of the process technology. Figure 2 uses Equation (3) to calculate optimal line width. We compare line widths obtained using Equation (3) to the optimal line widths as found by sweeping W in GTX, for a range of driver and interconnect topologies. In addition, we incorporate ....

S. P. Khatri, A. Mehrotra, R. K. Brayton, A. SangiovanniVincentelli, and R.H.J.M. Otten, "A Novel VLSI Layout Fabric for Deep Submicron Applications," Proc. DAC, 1999, pp. 491-496.

....of technology dependent optimization with placement. We show our experimental results in Section 6. Finally, we conclude in Section 7. 2 Technology and Net Models 2. 1 Technology Parameters For this paper, we use the 0 1m strawman process technology developed by Khatri and Mehrotra [8]. Table 1 shows the parameters for this 0 1m technology (for metal layers 1, 2, 3, and 4) Also listed in the table are the resistance per square and capacitance per micron (of a minimum width wire) The capacitance value is the sum of the line to line (lateral) capacitance and the capacitance ....

S Khatri, A Mehrotra, R Brayton, A Sangiovanni-Vincentelli, and R Otten. A novel VLSI layout fabric for deep sub-micron applications. In DAC, New Orleans, June 1999.

....in a loss of signal integrity. With the decreasing minimum feature size of VLSI fabrication processes, these problems are becoming increasingly common [1] In this paper, we present a design flow to alleviate the cross talk problem. Our scheme is motivated by the fabric concept introduced in [2]. In both approaches, the cross talk problem is eliminated by design. This is done by imposing a fixed pattern of wires on the IC die, on all metal layers. In particular, this repeating pattern, henceforth referred to as the Dense Wiring Fabric (DWF) is 34343 VSGSVSGS 34353 , where V ....

....ensures that adjacent signal wires are always capacitively shielded from each other. Metal wires on any layer run perpendicular to those on layers above and below it. This layout arrangement is shown in Figure 1. S S S S S V V G G S G S V S G S Figure 1: Arrangement of conductors as in [2]. As reported in [2] the use of this fabric has some compelling advantages. First, with this choice of layout fabric, the cross coupling capacitance between signal wires drops by one to two orders of magnitude, thereby all but eliminating the delay variation and signal integrity problems due to ....

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S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, and R. Otten, "A novel VLSI layout fabric for deep sub-micron applications," in Proceedings of the Design Automation Conference, (New Orleans), June 1999.

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S. Khatri et al. "A novel VLSI layout fabric for deep sub-micron applications," Proc. of DAC 1999, pp. 491-496, June 1999.

No context found.

Khatri, S.P., Mehrotra, A., Brayton, R.K., Sangiovanni-Vincentelli, A.L., and Otten, R.H.J.M. A novel VLSI layout fabric for deep submicron applications, in Proc. Design Automation Conference, June 1999, 491-496.

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S. Khatri, A. M. Mehrotra, R. K. Brayton, and A. Sangiovanno-Vincentelli, "A novel VLSI layout fabric for deep sub-micron applications," in DAC, 1999.

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S. P. Khatri, A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli and R. H. J. M. Otten, "A Novel VLSI Layout Fabric for Deep Sub-Micron Applications", Proc. 36th Design Automation Conf., 1999, pp. 491-496.

No context found.

S. P. Khatri, A. Mehrotra, R. K. Brayton, A. SangiovanniVincentelli, and R.H.J.M. Otten, "A Novel VLSI Layout Fabric for Deep Submicron Applications," Proc. Design Automation Conference, 1999, pp. 491-496.

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