P.C. Maulik, "Formulations for Optimization-Based Synthesis of Analog Cells," Carnegie Mellon University, Research Report CMUCAD-92-50, October 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....r r rr rrrr rrrrr r XYV X X E Area Y X Yield Y X V PYXV P st s s 2 (1) Where, binary vector r Y represents the circuit topology . In another word, if y i (the i th component of vector r Y ) is one, then block B i is included in the circuit, and B i is taken away while y is zero[1,2]. Continuous vector r V denotes the bias voltages, r X denotes device sizes and r r s X 2 is the variance of r X . Function Yield ( and Area ( represent the yield and the area of the circuit respectively. Function r P( is the performance of the circuits, which is composed of ....

....All of them include two steps: topology selection and parameter selection (also called device sizing) In another word, these analog synthesis systems determine r Y at first, then r X and r V . Sponsored by China Ph.D. Foundation ED TC 96 0 89791 821 96 5.00 1996 IEEE P.C. Maulik[1,2] employ NPSOL[9] and branch and bound algorithm[10] to do topology selection and device sizing simultaneously, however it can not realize a real simultaneous topology selection and device sizing[3] The Maulik s method also falls short in finding a global minimum of the MINLP problem (1) In this ....

Maulik P.C., "Formulations for Optimization-Based Synthesis of Analog Cells," Research Report No. CMUCAD-92-50, Carnegie Mellon Univ., Oct. 1992.

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P.C. Maulik, "Formulations for Optimization-Based Synthesis of Analog Cells," Carnegie Mellon University, Research Report CMUCAD-92-50, October 1992.

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