M. Abramovici and P. R. Menon, "A practical approach to fault simulation and test generation for bridging faults," IEEE Transactions on Computers, vol. C-34, no. 7, pp. 658--663, July 1985. 16  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... [Pancholy 90] Maxwell 91] Storey 91] Perry 92] Gayle 93] Ma 95] In order to achieve the quality levels now required for digital integrated circuits, research has been done on deterministic test pattern generation and fault simulation techniques that explicitly target bridging faults [Abramovici 85] Acken 91] Millman 91] Lee 91] Ferguson 91] Hajj 92] Greenstein 92] Chess 93, 94] Rearick 93] Maxwell 93] While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo random testing of bridging faults. Pseudo random testing is an ....

....faults are detected. One issue is the amount of time that is required for fault simulation of the bridging faults. One advantage of using gate level bridging fault models is that a stuck at fault simulator can be used for fault simulation of bridging faults as described by Abramovici and Menon [Abramovici 85] This is done by using the theorems listed above to relate bridging fault detection to stuck at fault detection. Each time a stuck at fault is detected, the theorems above are used to determine which bridging faults to mark as detected. Normally a stuck at fault is dropped from the fault list ....

Abramovici, M., and P.R. Menon, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults," IEEE Transactions on Computers', Vol. C-34, No. 7, pp. 658-663, Jul. 1985.

....node is connected. In reality, not only do different gates have different thresholds, but each input of a gate has a different threshold [6] 7] It is well known that the stuck at fault model is inadequate for modeling bridging faults [8] 9] Many models have been developed for bridging faults [6][10][11] 12] 13] 14] 15] 16] Most of these fault models assume a zero ohm bridge resistance, but several models assume a resistive bridge [3] 17] 18] 19] 20] As shown in [1] many bridges can have significant resistance. Figure 1 shows the bridging resistance distribution fit to the data in [1] R ....

M. Abramovici and P. R. Menon, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults," IEEE Trans. Computers, vol. 34, no.7 pp. 658-662, July 1985.

....mainly applicable to CMOS circuits is the voltage detectors method. Finally, these techniques are compared, emphasizing each method s advantages and disadvantages. 1.What are Bridging Faults Bridging faults (BFs) are caused by shorts between normally unconnected signal lines (Figure 1. a) [1]. This definition covers stuck on, latch ups and gate oxide shorts. Depending on the technology the lines connected by a BF can have a definite value or not. Different models for BF deal with different technology related behaviour, trying to describe more accurately the phenomenon. Considering a ....

....for large designs. 2.The Logic Approach Logic Testing for BF does not assume explicitly a fabrication technology because it uses the gate level description of the design. Still, the technology determines the fault model to be used. Most of the work done in this area uses simple wired models [1] [3] 6] For a certain circuit having G gates and I primary inputs the number of possible faults is BFs affecting only 2 lines. For G I, b G 2 which even for small designs is rather big and the fault simulation becomes prohibitive in terms of time. In practice the number of feasible BFs is ....

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M. Abramovici and P.R. Menon, "A practical approach to Fault Simulation and Test Generation for Bridging Faults," IEEE Trans. on Computers, Vol. C-34, No.7, pp. 658-663, July, 1985.

....pair to be unconnectable. Given the two classes of line pairs and the two defect types, we assume 4 fault classes which are previously presented in [10] The interconnect faults which we target are subsets of bridging faults whose detection requirements have been outlined in previous work [12] [2]. We summarize the 4 fault classes here. Permanent Connection (PC) A short on any pair of lines. Both affected lines must be separately controllable and at least one affected line must be observable. Also, any PIP between the two affected lines must be configured to be off. Permanent ....

M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34(7):658--663, July 1985.

....line pair to be unconnectable. Given the two classes of line pairs and the two defect types, we assume 4 fault classes which are previously presented in [10] The interconnect faults which we target are subsets of bridging faults whose detection requirements have been outlined in previous work [15, 2]. We summarize the 4 fault classes and the detection requirements for each class in terms of the controllability and observability of each line involved. Permanent Connection (PC) A short on any pair of lines. Both a ected lines must be separately controllable and at least one a ected line ....

M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34(7):658-663, July 1985.

....28(a) On the other hand some faults that may occur considering the gate implementation of the circuit, do not exist in the physical circuit; this is the case of the short number 5 of Figure 28(b) 4. 2 Bridging Faults The problem of bridging fault has been extensively treated by several authors [1, 5, 17, 23]. In general we may distinguish between two types of bridging faults: non feedback and feedback bridging faults. A bridging fault occurs when two or more lines in the circuit are wired together. There are two types of bridging faults: ffl AND bridging faults, when two or more lines are shorted ....

M. Abramovici, P.R. Menon, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults", IEEE Trans. on Computers, vol. C-34, n.7, pp.658---633, July 1985.

....model isolated faults. 4.1 Wired logic The wired logic model (wired AND or wired OR) is the easiest model to implement for simulation and test pattern generation. It has the benefit of speed; the wired logic model closely resembles the single stuck at fault model with a few additional constraints [AM85] When the idea of test generation for bridges was new, the assumption that the bridges caused wired AND or wired OR behavior was fairly good. In the dominant technologies of the time (such as TTL) bridges did create wired logic. However, wired logic does not accurately reflect the behavior of ....

.... (although still inferior to that of tests generated using the two component model [CL94] This improvement requires a much smaller programming effort than that required to generate tests with the twocomponent model because wired AND test generation is very similar to stuck at test generation [AM85] Simulation is conceptually simpler than test generation, and the effort required to create a sophisticated simulator is far below that required to create an equally sophisticated test generator [CL93] The small amount of improvement can be partly attributed to our experimental setup, which did ....

M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34:658--663, 1985.

....The PBF in Figure 1 is the one used if the technology in question follows the wired AND model, and Figure 2 shows a PBF derived from circuit analysis of the CMOS MCNC standard cell components. Many people have chosen the PBF to be the logic AND or logic OR of the two fault free gate outputs [1, 9, 12]. These models are inaccurate for CMOS circuits, where the PBF will vary depending on the size, function, and technology of the bridged components. The voting model or an analog circuit analysis might be used to determine a more accurate Primitive Bridge Function [2, 3, 4] It is possible that the ....

....combinational circuit may oscillate or take on sequential characteristics that mask the detection of the fault. It is possible to detect some feedback bridge faults that create sequential behavior with sequences of test vectors [12] but we have found that, as reported by Abramovici and Menon [1], the vast majority of feedback bridge faults can be detected with a single combinational test. Previously, explicit bridge fault simulation was thought to be unwieldy because of the number of feasible bridge faults and the complexity of the bridge fault model. While the number of possible bridge ....

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M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34:658--663, 1985.

....the Byzantine Generals problem [AM92] The wired logic model (wired AND or wired OR) is the easiest model to implement for simulation and test pattern generation. It has the benefit of speed; the wired logic model closely resembles the single stuck at fault model with a few additional constraints [AM85]. The wired logic model assumes that one of either the nmos or pmos networks will always determine the circuit s result. It is relatively easy to present examples in real circuits where this is not the case [FL91, GP92] A better model would assume that the circuit value at the fault site is ....

....V 5.00 V 3.00 V Figure 6: A non oscillating feedback bridge fault [CL93] For wired logic, the issue of a bridge fault creating feedback is easy to deal with. When we consider the wired AND model, if the fault appears on the back wire, and it sensitizes the front wire, the circuit may oscillate [AM85]. All we need to do is disallow tests in which the front wire is sensitized to the back wire. Similar arguments can be made for wired OR tests invalidated by sequential behavior. More general arguments can be made for any possible Boolean bridge function [CL93] These methods of dealing with ....

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M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34:658--663, 1985.

....In the process of modifying Nemesis to handle these additional faults, we have improved both our algorithmic test pattern generation and our fault simulation routines. For the larger benchmark circuits, our bridge fault simulation techniques offer a significant advancement over existing methods [AM85] As we work on the integrated Carafe Nemesis system, there are some improvements we are considering that affect only Nemesis (and not Nemesis s interface with other software in our system) Below we consider two enhancements to the Nemesis system: Improvements to the Satisfier (the back end of ....

M. Abramovici and P.R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C34 (7):658--663, July 1985.

....1 Introduction It is known that the bridging faults (BFs) are the major failure source of the VLSI circuits. This kind of fault is due to the failure of two or more leads unintentionally shorted. It has been shown that a bridging fault is hard to be modeled using the stuck at fault model [1, 2]. There are two testing methodologies being used to test bridging faults. First, logic function test technique determines test results by measuring the output voltage of CUT [1, 2, 3] The faulty behavior of a cell with a bridging fault can be determined using simulation and the results can be ....

....unintentionally shorted. It has been shown that a bridging fault is hard to be modeled using the stuck at fault model [1, 2] There are two testing methodologies being used to test bridging faults. First, logic function test technique determines test results by measuring the output voltage of CUT [1, 2, 3]. The faulty behavior of a cell with a bridging fault can be determined using simulation and the results can be used to sensitize the cell s inputs to the output [3] The voltage thresholds are needed to be assumed. Second, I DDQ testing technique determines the test results by monitoring ....

M. Abramovici and P. Menon, "A practical approach to fault simulation and test generation for bridging faults," in Proc. Int'l Test Conf., pp. 138--142, 1983.

....fault may cause oscillation, which may prevent a tester from detecting a discrepancy at the circuit outputs. Most approaches for testing feedback bridge faults check for tests invalidated by oscillation or sequential behavior by analyzing the inversion parity between the two bridged wires [1, 12]. Previous successful bridge fault test pattern systems notably that of Millman and Garvey [12] generate a test as if there is no feedback and then check to make sure that feedback will not invalidate the test. But oscillation and sequential behavior do not need to be prevented by performing a ....

M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34:658--663, 1985.

....inter cell BFs are jointly named adjacency BFs. An intra cell BF involves two internal nets within the same cell. Existing work on bridging fault simulation can be divided into the following five types: gate level, switchlevel, electrical level, mixed level, and table based. Gate level simulators ([3, 4], to mention a few) employ either wired and or wired or logic to represent a BF so that the fault simulation can be done at the gate level speed. However, it was pointed out in [5, 6] that the circuit behavior under a BF could not be well modeled by permanent wired logic. Therefore a better BF ....

M. Abramovici and P. Menon, "A practical approach to fault simulation and test generation for bridging faults," IEEE Transactions on Computes, pp. 658--663, 1985.

....at very low CPU time and memory costs as compared with the flat approach, such as CARAFE. III. BRIDGING FAULT SIMULATION Existing work on BF simulation can be divided into the following five types: gate level, switch level, electricallevel, mixed level, and table based. Gate level approaches ([11, 12], to mention a few) employ either wired and or wired or logic to model the bridged gates so that the BF simulation can be done efficiently at gate level. However, 13, 14] pointed out the inadequacy of using the wired logic models and suggested the use of Primitive Bridge Functions (PBFs) as ....

M. Abramovici and P. Menon, "A practical approach to fault simulation and test generation for bridging faults," IEEE Transactions on Computers, pp. 658--663, 1985.

....this case extensive analysis may be required to ensure not only that the feedback element can hold state, but that it is guaranteed to hold state. It can be dangerous to assume that the state element introduced by the fault will achieve a stable digital value. As reported by Abramovici and Menon [1], the vast majority of feedback bridging faults can be detected with single combinational tests. When discussing feedback bridging faults, it is useful to refer to the two bridged wires by their locations in the circuit. Given any path that goes from a circuit input to a circuit output and ....

....dominant technologies of the time (such as TTL) bridging faults did create wired logic. Abramovici and Menon detailed complete theories and techniques to perform ATPG on bridging faults (including bridging faults that introduced feedback) in combinational circuits exhibiting wired logic behavior [1]. However, wired logic does not accurately reflect the behavior of bridges in static CMOS circuits [4, 12, 20] The wired logic model (wired AND or wired OR) is the easiest model to implement for simulation and test pattern generation; with the exception of feedback, the wired logic model is ....

[Article contains additional citation context not shown here]

M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34:658--663, 1985.

....would consider computing ab m j =00 if and only if ab f00g i 6= 0. Similar corollaries hold for ab f01g i , ab f10g i , and ab f11g i . Oscillating perturbations. When perturbations introduce a cycle, we can observe effects similar to the feedback bridging faults reported in [8]. Oscillating perturbations as defined here are analyzed in more detail in [1] We refer to a k in p perturbation as a cyclic perturbation if there is at least one path between p and k wires. If there is no such path, the perturbation is denoted as an acyclic perturbation or simply a ....

M. Abramovici and P. R. Menon. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. on Comp., C-34(7):658--663, July 1985.

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M. Abramovici and P. R. Menon, "A practical approach to fault simulation and test generation for bridging faults," IEEE Transactions on Computers, vol. C-34, no. 7, pp. 658--663, July 1985. 16

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M. Abramovici and P. R. Menon, "A practical approach to fault simulation and test generation for bridging faults," IEEE Trans. Comput., vol. C-34, pp. 658--663, July 1985.

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M. Abramovici and M. Breuer. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. on Computers, C-34(7):658--663, July 1985.

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