TSENG, J. H., AND ASANOVIC, K. Energy-efficient register access. In Proceedings of the 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00) (2000), IEEE Computer Society, p. 377.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....partitioned register files have been proposed to support clusters of functional units [5,7] There are a few circuitlevel techniques for low energy register files. For ultra low energy dissipation, the NRERL register file is an adiabatic register file clocked at less than 1 MHz [11] In [16], the Table 1: Register file technique pipline interaction summary: previous proposals (left) and ours (right) 2 level: Rename: Search active list to update usage Rollback: Search copy list to restore L2 entries to L1 Register Caching: Issue: Pre read operands and store in issue queue. ....

J. Tseng and K. Asanovic. Energy-efficient register access. In Proc. XIII Symposium on Integrated Circuits and Systems Design, Sept. 2000.

....gating. 4.3 Register File The register file and bypass network consume around 40 of the unoptimized datapath energy. In this section I analyze several techniques for reducing register file reads and switching activity in the bypass network. Most of these techniques were previously presented in [44], but the analysis in this section is based on my implementation of the optimizations in the SyCHOSys processor simulation. In the base case, every instruction reads two operands from the register file; however, many of these values are never used. Precise read control (PRC) eliminates reads ....

....The upper plots show bit activity per read for the rx and ry read ports using a standard storage cell, and the lower plots show the activities using a modified storage cell. storage cell many of the rx read port bits transition almost twice per read. Amodified storage cell (MSC) is described in [44]. With minimal overhead, this design reads inverted data for rx in addition to ry, so that none of the register file bitlines discharge when zero bits are read from the register file. The lower half of Figure 4 10 shows the dramatic reduction in bit activity for the rx read port; its activity ....

J. Tseng and K. Asanovic. Energy-efficient register access. In Proc. XIII Symposium on Integrated Circuits and Systems Design, Manaus, Brazil, September 2000.

....obtained from HSPICE simulations of extracted layout with 2.5V supply voltage. We obtained relative leakage energy numbers by calculating the total width of leaking transistors assuming that 70 of stored values are zero, and the bit cell ports were optimized to reduce read energy for zero values [19]. For the fully ported storage cell designs, using hierarchical bitlines reduces energy by almost 40 and cuts delay by 8 17 . The lesser ported bank designs have a slightly greater reduction in delay, at around 25 faster for the two read, two write port case. The energy reduction is also ....

J. Tseng and K. Asanovic. Energy-efficient register access. In Proc. of the 13th Symposium on Integrated Circuits and Systems Design, Manaus, Brazil, September 2000.

....single ended read ports. The write ports are not as latency critical and so these access transistors are high V T . To reduce active and leakage energy further, we make the cell asymmetrical, with all read ports arranged so that if the cell stores a zero, the single ended bitline is not discharged [31]. Our experiments showed that around 75 of the bits read from the register file are zero. WRITE[0:3] WWL[0:3] WRITEB[0:3] RWL[0:7] X8X8 X4X4 X4 READ[0:7] Figure 6. An embedded dual V T unbalanced 8 read, 4 write register file cell. High V T transistors As with the cache SRAM, the ....

J. Tseng and K. Asanovic. Energy-efficient register access. In Proc. of the 13th Symposium on Integrated Circuits and Systems Design, Manaus, Brazil, September 2000.

....discharged based on the stored data bit. Register files are often built with single ended read ports to reduce total wiring cost. The register file bit cell can be modified so that reading a zero on any port causes no bitline discharge, resulting in a savings of 27 of total register file energy [10]. Chang et al. 12] describe another scheme for ROMs and small RAMs with single ended bitlines that conditionally inverts stored words to reduce the total number of bitline discharges, and achieves an average of 30 energy reduction for a RAM array. For larger SRAM array designs, differential ....

J. Tseng and K. Asanovic. Energy-efficient register access. In Proc. XIII Symposium on Integrated Circuits and Systems Design, Manaus, Brazil, September 2000.

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TSENG, J. H., AND ASANOVIC, K. Energy-efficient register access. In Proceedings of the 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00) (2000), IEEE Computer Society, p. 377.

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