F. Paillet, D. Mercier and T.M. Bernard, "Making the most of 15k lambda2 silicon area for a digital retina PE," Proc. SPIE, Vol. 3410, Advanced Focal Plane Arrays and Electronic Cameras, pp. 158-167, 1998. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Improved Low Complexity Fully Parallel Thinning Algorithm - Bernard, Manzanera (1999) (2 citations) Self-citation (Bernard) (Correct)
....is still the reference in the field of Boolean complexity. The Shannon complexity of a data parallel procedure represents its minimal execution time on a basic cellular automata machine, such as the one developed in cooperation with the authors, under the form of a Programmable Artificial Retina [13]. However, the Shannon measure makes sense for any software or hardware implementation as it is related to Area Time complexity. It also represents the minimal amount of energy required to perform the computation of a digital function, as every operation between two bits of information physically ....
F. Paillet, D. Mercier and T.M. Bernard, "Making the most of 15k lambda2 silicon area for a digital retina PE," Proc. SPIE, Vol. 3410, Advanced Focal Plane Arrays and Electronic Cameras, pp. 158-167, 1998.
Second Generation Programmable Artificial Retina - Paillet, Bernard (1999) Self-citation (Paillet Mercier Bernard) (Correct)
....bit requires two CMOS inverters in a loop with some select circuitry: at least 6 transistors. With fifty to one hundred transistors in the PE, M is necessarily small. As such, M strongly conditions the processing abilities of the PE. Maximising M is therefore crucial. For this reason, we have used [12] semi static binary registers (SSBRs) to store binary data rather than standard static RAM cells [9,10] The main feature of SSBRs is that they can be easily linked to form shift registers, as shown on Fig. 1a. Note that a single nMOS transistor is used as pass gate between pairs of inverters in ....
....cost is 49 transistors, 9 minimal width wires for control and two larger wires for ground and power supply. The size of all transistors is small, generally minimal. then to get it back) The point is to further compute A B with the help of an inverter but without the need of a third register [12], thus achieving a better use of the PE memory capacity M. This is all the more important as M is small. It can be crucial for temporal processing, e.g. motion analysis, which needs to store results from the past. A short example that also illustrates this, is to compare the largest counter that ....
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F.Paillet, D.Mercier and T.M.Bernard, "Making the most of 15k lambda2 silicon area for a digital retina PE", Proc. SPIE 3410, Adv. Focal Plane Arrays and Electronic Cameras, pp.158-167, 1998.
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