Ishikawa M, Ogawa K, Komuro K, Ishii I. A CMOS vision chip with SIMD processing element array for 1 ms image processing. Dig Tech Papers of 1999 IEEE Int Solid-State Circuit Conf (ISSCC'99), p 206--207. Home/Search Document Not in Database Summary Related Articles Check |
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Second Generation Programmable Artificial Retina - Paillet, Bernard (1999) (Correct)
....6. However, transistor cost would be at least 120 using a tree structure (about 80 nMOS and 40 pMOS) thus doubling PE transistor count, while the power consumption for driving the row control wires would triple. Though intermediate solutions are possible, as well as time multiplexed ones [10], the lesson we learn from this case is that avoiding any instruction decoding is really worth some effort. Section 2B explains how we have managed to do so while maintaining a good balance between wiring and logic. Anyway, the result is that the PVLSAR2.2 PE is a pure datapath. And so is the ....
....to one hundred transistors in the PE, M is necessarily small. As such, M strongly conditions the processing abilities of the PE. Maximising M is therefore crucial. For this reason, we have used [12] semi static binary registers (SSBRs) to store binary data rather than standard static RAM cells [9,10]. The main feature of SSBRs is that they can be easily linked to form shift registers, as shown on Fig. 1a. Note that a single nMOS transistor is used as pass gate between pairs of inverters in order to save area (how it is possible will be explained thereunder) Each SSBR may belong to several ....
M.Ishikawa et al., "A CMOS vision chip with SIMD processing element array for 1ms image processing", Digest of Tech. Papers, ISSCC, pp 206-207, 1999.
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Ishikawa M, Ogawa K, Komuro K, Ishii I. A CMOS vision chip with SIMD processing element array for 1 ms image processing. Dig Tech Papers of 1999 IEEE Int Solid-State Circuit Conf (ISSCC'99), p 206--207.
Book Title - Book Editors Ios Self-citation (Ishikawa Ogawa) (Correct)
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M. Ishikawa, K. Ogawa, T. Komuro and I. Ishii. A CMOS vision chip with SIMD processing element array for 1 ms image processing. Dig. Tech. Papers of 1999.
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M. Ishikawa, K. Ogawa, T. Komuro, and I. Ishii, "A CMOS vision chip with SIMD processing element array for 1 ms image processing," in Dig. Tech. Papers IEEE Int. Solid-State Circuit Conf., 1999, pp. 206--207.
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M. Ishikawa, K. Ogawa, T. Komuro, and I. Ishii, "A CMOS vision chip with SIMD processing element array for 1 ms image processing, " in Dig. Tech. Papers of 1999.
Motile Cell Galvanotaxis Control Using High-Speed.. - Ogawa, Oku, Hashimoto, .. (2004) Self-citation (Ishikawa Ogawa) (Correct)
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M. Ishikawa, K. Ogawa, T. Komuro, and I. Ishii, "A CMOS vision chip with SIMD processing element array for 1ms image processing, " in Dig. Tech. Papers of 1999.
Adaptive Dynamics Matching in Sensory-Motor Fusion . . . - Ogawa Self-citation (Ishikawa Ogawa) (Correct)
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M. Ishikawa, K. Ogawa, T. Komuro, and I. Ishii: "A CMOS vision chip with SIMD processing element array for 1ms image processing," 1999.
Single-Cell Level Continuous Observation of.. - Ogawa, Oku.. (2004) Self-citation (Ishikawa Ogawa) (Correct)
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M. Ishikawa, K. Ogawa, T. Komuro, and I. Ishii, "A CMOS vision chip with SIMD processing element array for 1ms image processing," in Dig. Tech. Papers of 1999.
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M. Ishikawa et al. A CMOS vision chip with SIMD processing element array for 1ms image processing. Dig. Tech. Papers of IEEE Int. Solid-State Circuits Conf., pages 206--207, 1999.
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