F.Paillet, D.Mercier, T.M.Bernard and E. Senn, "Low power issues in a Programmable Artificial Retina", Proc. IEEE Workshop on Low Power Design, pp.153-161, 1999.  Home/Search   Document Not in Database   Summary   Related Articles

.... In this paper, we show an example of what can be already done with about 50 transistors per pixel. We have used them to process and analyse images where they are sensed. Our prime design criterion has been to get the best possible algorithmic versatility without neglecting power consumption [5]. We have actually designed, tested and operated a 128 128 CMOS imager in which each pixel contains a tiny digital processing element (PE) It is the largest ever reported in the literature, though it has been fabricated in a standard and quite outdated 0.8 m CMOS process. We have called it ....

....drawbacks are concerned, the structure of Fig. 1c significantly improves [11] over that used in [6] Besides, regarding power consumption, the massive parallelism available in such an array processor makes it acceptable to operate below maximal clock frequency, thus allowing low voltage operation [5] (see section 2F) SSBRs would loose much of their interest if it were not possible to connect them through single nMOS transistors used a pass gates. The danger with such a solution is signal degradation when transmitting a logical one. To avoid this problem, two different power supplies are ....

[Article contains additional citation context not shown here]

F.Paillet, D.Mercier, T.M.Bernard and E. Senn, "Low power issues in a Programmable Artificial Retina", Proc. IEEE Workshop on Low Power Design, pp.153-161, 1999.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC