Dobbelaere, I., Horowitz, M., El Gamal, A. \Regenerative Feedback Repeaters for Programmable Interconnections," IEEE Journal of Solid-State Circuits, Vol. 30 No. 11, pp. 1249-1253, November 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....its size (which determines the resistance and the parasitic capacitance, if important) the long interconnection paths between macroblocks, and the prospective load to drive after each interconnection. The problem of the interconnection in programmable devices has attracted attention recently [2]. As studied by Weste and Eshraghian [3] an aproximate discrete analysis of a line modelled as RC cascadated sections (of equal R and C) yields t RCn n n ( 1 As it can be seen from the equation above, the total delay depends quadratically on the number of sections and linearly on ....

....dealing with switching matrix based FPGAs, in which long paths crossing several interconnections take place, producing big delays that grow fastly. New methods have been pointed out to minimize this problem, for instance placing regenerative feedback repeaters at a given number of interconnections [2]. Nevertheless, a tradeoff for the switch size must be reached in order to obtain an optimal result. The bigger the switch the smaller the resistance, but too big a switch will incur a high area penalty and parasitic capacitance. Optimization methods have been proposed in order to achieve a good ....

Ivo Dobbelaere, Mark Horowitz and Abbas El Gamal, "Regenerative Feedback Repeaters for Programmable Interconnections", IEEE Journal of Solid-State Circuits, Vol. 30, N. 11, November 1995.

....Pass Gate Accelerators Like the Abacus 1 design, Abacus 2 incorporates accelerators to reduce the quadratic delay growth with the number of pass switches. Unlike the noiseintolerant NORA based accelerator described in Chapter 3, the new design uses a slightly slower but more robust static circuit (Dobbelaere, Horowitz Gamal 1995). Global OR Unlike the Abacus 1 design, PEs can no longer be joined into one large electrically connected net. Specialized global OR circuitry is therefore provided. The precharged carry circuitry is optionally connected to a dedicated column wire. The eight columns are reduced to a single bit by ....

Dobbelaere, I., Horowitz, M. & Gamal, A. E. (1995), Regenerative Feedback Repeaters for Programmable Interconnections, in `International Solid State Circuits Conference', IEEE.

....topologies that were used for the conventional repeaters and for the regenerative feedback repeaters, respectively, for delay comparison. The topology for the conventional repeaters is less general than the topology for the regenerative feedback repeaters and than the one we considered before in [11], but it is appropriate in a comparison directed toward FPGA s. Fig. 10 shows the circuit schematic of the tristate buffer used in the conventional repeater. The buffer threshold was 2.0 V. Fig. 11 compares delays per stage, expressed in units of equivalent per stage, for simulations of the ....

I. Dobbelaere, M. Horowitz, and A. El Gamal, "Regenerative feedback repeaters for programmable interconnections," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 116--117.

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Dobbelaere, I., Horowitz, M., El Gamal, A. \Regenerative Feedback Repeaters for Programmable Interconnections," IEEE Journal of Solid-State Circuits, Vol. 30 No. 11, pp. 1249-1253, November 1995.

No context found.

I. Dobbelaere, M. Horowitz, and A. El Gamal, "Regenerative feedback repeaters for programmable interconnections," IEEE Journal of Solid-State Circuits, vol. 30, no. 11, 1995.

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