C.-Y. Hwang, Y.-C. Hsieh, Y.-L. Lin, and Y.-C. Hsu. A fast transistor chaining algorithm for CMOS cell layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 9:781--786, July 1990. Home/Search Document Not in Database Summary Related Articles Check |
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Transistor Chaining with Integrated Dynamic Folding for 1-D.. - Berezowski (Correct)
....and uses transistor chaining as its basic width reduction technique. This approach succeeded in finding the efficient heuristics [4, 21] as well as computationally tractable exact algorithms either for the restricted class of dual series parallel circuits [19] or for dual unrestricted circuits [16]. Unfortunately, if more layout characteristics than just a cell width is to be optimized (i.e. routing channel height) even the simplest formulation of the problem becomes NP hard [5] With growing importance of the performance driven circuit design the leaf cell synthesis problem has been ....
C.-Y. Hwang, Y.-C. Hsieh, Y.-L. Lin, and Y.-C. Hsu. A fast transistor chaining algorithm for CMOS cell layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 9:781--786, July 1990.
A Combined Pairing and Chaining Algorithm for CMOS.. - Velasco, Marn.. (1996) (Correct)
....the number of diffusion gaps, and hence, the overall area. Previous Approach The optimization problem of chaining has been widely studied and some approaches have been presented to find optimal solutions given a fixed pairing. Perhaps the most versatile algorithm was presented by Chi Yi Hwang in [1]. Here, the chaining process is divided into separate steps: pairing, bipartite graph construction and chain formation. Pairing is responsible for grouping transistors into fixed pairs. Following heuristical criteria, the pairing process generates a set of pairs that involve each transistor once. ....
C. Y. Hwang, Y. C. Hsieh, Y. L. Lin and Y. C. Hsu, "A Fast Transistor-Chaining Algorithm for CMOS Cell Layout." IEEE Trans. CAD, n 7, pp. 781-786, July 1990.
Transistor Chaining with Integrated Dynamic Folding - For Leaf Cell (2001) (Correct)
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C.-Y. Hwang, Y.-C. Hsieh, Y.-L. Lin, and Y.-C. Hsu. A fast transistor chaining algorithm for CMOS cell layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 9:781--786, July 1990.
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