R. van de Plassche, Integrated analog to digital and digital to analog converters, Kluwer Academic Publishers, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of a comparator is affected by digital noise. In this section we will derive conclusions about the effect of the substrate noise on an embedded ADC, based on the knowledge from the measurements on the comparator. One of the main problems in the design of high speed ADCs is the clock jitter [1] [9]. It affects the ADC by changing the time when the input signal is sampled. The jitter on a comparator output that we measured above due to substrate noise is different in the sense that it does not modify the sampling time but affects the time characteristic of the comparator, the delay for ....

R. Van De Plassche, "Integrated Analog-to-Digital and Digital-to-Analog Converters", ed. Kluwer Academic Publishers, 1992.

....This is a deterministic error, if the input signal is known. But for most signals it can be treated as additive white noise uncorrelated with the input signal and with uniform distribution [10] Random jitter Due to noise in the clock signal there is a random error on the sampling instances [11]. These errors can be treated as Gaussian white noise on the sampling instances. II. NOTATION AND DEFINITIONS We will in this section introduce the notation that will be used in this paper. The nominal sampling interval, that we would have without time errors, is denoted T s . M denotes the ....

R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994.

....processing, it has the disadvantage of large power consumption and high input capacitance as the number of comparators increases exponentially with the resolution specification. To overcome these shortcomings, analog preprocessing like interpolating, folding and averaging is usually applied [5]. The interpolating averaging architecture is depicted in Fig. 2. The front end is fully differential for improved dynamic performance. A Sample Hold circuit (S H) samples the differential input signal. The resulting signal is compared and amplified with the fully differential reference ladder ....

....0.9 1.0 Preamplifier Bandwidth Input Frequency V V GS T Figure 3: HD3 as a function of the preamplifier bandwidth input frequency ratio for a V fs of 1.25 V. Apart from the mismatch constraint, the admissible phase shift for the preamplifier is also determined in this stage of the design. In [5] a formula was derived for the resulting third order distortion HD 3 as a function of the bandwidth of the preamplifier stages: 1 2 3 where , 3 # # b fs in T GS n f V f V V b b in e g f f g HD (3) V fs is the full scale input range, f in is the input frequency and f b ....

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R. Van de Plassche, "Integrated Analog-To-Digital and Digital-To-Analog Converters", Kluwer Academic Publishers, ISBN 0-7923-9436-4, p. 193-204, 1994.

....is a deterministic error, if the input signal is known. However, for most signals it can be treated as additive white noise uncorrelated with the input signal and with uniform distribution [4] Random jitter Due to noise in the clock signal there is a random error on the sampling instances [5]. These errors can be treated as Gaussian white noise on the sampling instances. II. NOTATION AND DEFINITIONS We will in this section introduce the notation that will be used in this paper. The nominal sampling interval, that we would have without time errors, is denoted T s . M denotes the ....

R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994.

....Then the power spectrum of u[k] is defined as [4] Ru [n]e j#n (4) The next two definitions are used to measure the performance of the ADC system. Assume that the measured signal y[k] consists of a signal part s[k] and a noise and distortion part e[k] y[k] s[k] e[k] 5) Then the SNDR [5] (Signal to Noise and Distortion Ratio) for y[k] is defined as (6) Assume that y[k] s[k] e[k] s[k] and e[k] are given by s[k] a sin(#0k) e[k] b i sin(# i k) e[k] 7) where e[k] is non periodic. Then the SFDR [5] Spurious Free Dynamic Range) for y[k] is defined as SFDR=10log ....

....and a noise and distortion part e[k] y[k] s[k] e[k] 5) Then the SNDR [5] Signal to Noise and Distortion Ratio) for y[k] is defined as (6) Assume that y[k] s[k] e[k] s[k] and e[k] are given by s[k] a sin(#0k) e[k] b i sin(# i k) e[k] 7) where e[k] is non periodic. Then the SFDR [5] (Spurious Free Dynamic Range) for y[k] is defined as SFDR=10log 10 max i b (8) 3. MISMATCH NOISE In this section we will calculate the spectrum caused by gain and offset errors in a randomly interleaved ADC. To calculate the spectrum we will also need a probabilistic model of the ....

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R. van de Plassche, Integrated Analog-to-Digital and Digital-toAnalog Converters, Kluwer Academic Publishers, 1994.

....Figure 1: Presented systematic design flow for an interpolating averaging A D converter. 2. THE INTERPOLATING AVERAGING ARCHITECTURE The interpolating averaging architecture is shown in Fig. 2. Just as in the flash architecture, processing is fully parallel resulting in high sampling rates [3]. The front end is fully differential for improved dynamic performance. A Sample Hold circuit (S H) samples the differential input signal. The resulting signal is compared with the fully differential reference ladder network and amplified in the first amplification stage. The output of this ....

.... 110 101 10 Prearnplifier Bandwidth Input Frequency Figure 4: HD s as a function of the preamplifier bandwidth input frequency ratio for a Vys of 1.25 V. Apart from the mismatch constraint, the admissible phase shift for the preamplifier is also determined at this stage of the design. In [3] a formula was derived for the resulting third order distortion HD3 as a function of the bandwidth of the preamplifiers: 2b, Vas Vr)fi 1 Vfs fb HD3 = 2g fi. where = e (4) 3r fb g V is the full scale input range, f, is the input frequency andfb is the bandwidth of the preamplifier, g ....

[Article contains additional citation context not shown here]

R. Van de Plassche, "Integrated Analog-To-Digital and Digital-To-Analog Converters", Kluwer Academic Publishers, ISBN 0-7923-9436-4, p. 193-204, 1994.

....Then the power spectrum of u[k] is defined as [3] Ru [n]e j#n (4) The next two definitions are used to measure the performance of the ADC system. Assume that the measured signal y[k] consists of a signal part s[k] and a noise and distortion part e[k] y[k] s[k] e[k] 5) Then the SNDR [4] (Signal to Noise and Distortion Ratio) for y[k] is defined as (6) Assume that y[k] s[k] e[k] s[k] and e[k] are given by s[k] a sin(#0k) e[k] b i sin(# i k) e[k] 7) where e[k] is non periodic. Then the SFDR [4] Spurious Free Dynamic Range) for y[k] is defined as SFDR ....

....distortion part e[k] y[k] s[k] e[k] 5) Then the SNDR [4] Signal to Noise and Distortion Ratio) for y[k] is defined as (6) Assume that y[k] s[k] e[k] s[k] and e[k] are given by s[k] a sin(#0k) e[k] b i sin(# i k) e[k] 7) where e[k] is non periodic. Then the SFDR [4] (Spurious Free Dynamic Range) for y[k] is defined as SFDR = 10 log 10 max i b (8) 3. MISMATCH NOISE In this section we will calculate the spectrum caused by gain and offset errors in a randomly interleaved ADC. To calculate the spectrum we will also need a probabilistic model of the ....

[Article contains additional citation context not shown here]

R. van de Plassche, Integrated Analog-to-Digital and Digital-toAnalog Converters, Kluwer Academic Publishers, 1994.

....through transmitting more complex symbols instead of simple bits. However, applying these techniques is challenging, especially at high symbol rates, because they require greater voltage resolution and timing accuracy. There is a growing interest in applying these techniques at GSym s rates ([95], 84] and [91] Successful use of these techniques will demonstrate that the aggregate data rate can continue to improve with technology, even though channel bandwidth limitations may constrain the number of symbols per second transmitted and received. 165 Appendices A.1 Time Invariance of ....

R. Van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 1994.

....V signalpp, noisepp, LENOB = log 2 (V SNR,p p ) 2.3] The LENOB is similar to the Effective Number of Bits (ENOB) used to measure ADC and DAC resolution, defined in Equation 2. 4 as a function of the Signal to Noise and Distortion Ratio (SNDR) on an asynchronous full scale sine wave [24][26] The primary difference is that the LENOB uses synchronous p p noise samples at the peaks of the signal, while the ENOB uses asynchronous noise power. A minor difference is the factor of 1.22 in Equation 2.4, which represents the ratio of the RMS value of ideal quantization noise to the RMS ....

R. Van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 1994.

....becomes more demanding an extensive set of speci cations is necessary to provide all the needed information. In literature there are varying de nitions for the same performance indicators. Therefore, this chapter gives a survey of the most important performance measures based on literature study [19, 21, 45]. These indicators refer to both static and dynamic DAC behavior. 2.1 Static Speci cations Like any electronic circuit in operation a digital to analog converter exhibits transient e ects when a new input is applied and the system tunes in to the proper output. The static DAC response is ....

....2.3. FREQUENCY DOMAIN SPECIFICATIONS 17 and Eq. 2.4) becomes SNR dB = 10 log V 2 rms;signal V 2 rms;noise = 20 log V rms;signal V rms;noise : 2.5) In the following a short derivation of the SNR in relation to the number of bits is given. For a more detailed explanation see [45]. The quantization process introduces an irreversible error, see Fig. 2.2 b) Let q s = S out;LSB denote the quantization step and S j a signal level, which can be converted with no error. Then a signal with amplitude S j , qs 2 qs 2 , will be quantized into level S j . This ....

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Rudy van de Plassche. Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994.

....N is the number of bits of the digital input word, and S is a one to one function that maps a position in the sequence of consecutive code words to an value. Furthermore, by definition P 2 N 1 i=1 i = 0. Note that (1) is a weaker (but sufficient) definition compared to the one used in [1]. One of the terms that is used with regard to dynamic performance is SFDR, which is defined to be the ratio between the maximum signal component and the largest distortion component in the frequency domain. Another important dynamic specification is the signal to noise plus distortion (SINAD) ....

R.J. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, 1994.

....8 bit DA converter The calibration coefficients a 1 to a 4 can be implemented as multiplying DACs. Fig.4 shows an 8 bit DA converter for differential current signals. The currents on the positive input and the negative input are divided into binary parts using two cascode dividers [3]. Each binary part is switched to either the positive or the negative output using a differential pair. The circuit is configured in such a way that the differential input current is multiplied with the 2 s complement value of the 8 bit digital signal A[7 0] applied at the switches. The digital ....

R. v.d. Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Publishers, Boston / Dordrecht / London 1994

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R. van de Plassche, Integrated analog to digital and digital to analog converters, Kluwer Academic Publishers, 1994.

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R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994.

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R. van de Plassche, "Integrated Analog-to-Digital and Digital-to-Analog Converters", Kluwer Academic publishers, Boston, 1994.

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R. Van de Plassche, Integrated Analog-to-Digital and Digital-toAnalog Converters, Kluwer Academic, Boston, 1994.

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