Rau, B.R., Schlansker, M.S., and Tirumalai, P.P. Code generation schemas for modulo scheduled DO-loops and WHILE-loops. Technical Report HPL-92-47. Hewlett Packard Laboratories, 1992. Home/Search Document Not in Database Summary Related Articles Check |
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Properties of Rescheduling Size Invariance for Dynamic.. - Conte, Sathaye (Correct)
....correctness of execution on G new . 4. 3 Rescheduling Size Invariant Cyclic Code Most programs spend a great deal of time executing the inner loops, and hence the study of scheduling strategies for inner loops has attracted great attention in literature [23] 24] 25] 8] 26] 27] 28] [29]. Inner loops typically have small bodies (relatively fewer Ops) which 12 header bit pause optype 1 0 1 A 0 2 x B 0 4 x C 0 5 x D 1 0 0 E 0 1 x F 1 0 0 G 0 7 x H 0 63 1 0 2 A 0 2 x B 0 4 x C 0 5 x D 1 0 0 E 1 1 0 F 1 0 0 G 0 7 x H 0 63 rest of the Op Dynamic Rescheduling ....
....techniques presented previously. First, some discussion of the structure of modulo scheduled loops in presented, followed by an algorithm to reschedule modulo scheduled code. The section ends with a formal treatment to show the list encoded modulo scheduled cyclic code is RSI. Concepts from Rau [29] are used as a vehicle for the discussion in this section. Assumptions about the hardware support for execution of modulo scheduled loops are as follows. In some loops, a datum generated in one iteration of the loop is consumed in one of the successive iterations (an inter iteration data ....
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B. R. Rau, M. Schlansker, and P. P. Tirumalai, "Code generation schemas for modulo scheduled DO-loop and WHILE-loops," Tech. Rep. HPL-92-47, Hewlett-Packard Laboratories, Technical Publications Department, 1501 Page Mill Road, Palo Alto, CA 94304, 1992. 20
Code Generation Schema for Modulo Scheduled Loops - Rau, Schlansker, Tirumalai (1992) (45 citations) Self-citation (Rau Schlansker) (Correct)
....graph while the other (RecMll) is derived from latency calculations around circuits defining recurrences within the data dependence graph for the loop body. The actual H must be greater than or equal to the maximum of these bounds. A more detailed discussion of ResMlI and RecMH can be found in [9, 11, 5, 18]. Any legal H must be equal to or greater than MAX(ResMII, RecMII) Figure la displays the FORTRAN DO loop which we shah use as an example, and the corresponding intermediate representation using virtual registers. Figure lb lists the operations within the body of the loop and the lefthand column ....
....It is possible to generate code for modulo scheduled loops for each assumption regarding the choice of code generation technique and available hardware support. All four code schemas, depending on whether rotating registers, predicated execution, neither or both are present, have been studied [18], In thi paper we shall restrict our discussion to two of the four sets of code schemas. In code schema 1, only speculative code motion is supported. In code schema 4, that plus predicated execution and rotating register files are provided. All of the code schemas described below have two things ....
Rau, B.R., Schlansker, M.S., and Tirumalai, P.P. Code generation schemas for modulo scheduled DO-loops and WHILE-loops. Technical Report HPL-92-47. Hewlett Packard Laboratories, 1992.
Acceleration of First and Higher Order Recurrences on.. - Schlansker, Kathail (1993) (4 citations) Self-citation (Schlansker) (Correct)
....Note that the use of the EVR is not restricted to processors with hardware support for rotating registers. Compilation techniques using virtual rotating registers are suitable for conventional register files but require the replication of loop program text as described in a paper by Rau et al. [17]. A scalar value s (usually calculated repeatedly within the body of a loop) can be referenced using the notation s[i] Each time a remap(s) is executed, all values in the sequence shift upward so that each value s[i] prior to the execution of a remap is renamed as s[i 1] after the remap. Thus, ....
....on the ResMII or the RecMII of the loop. For example, it may appear that a loop body with n remaps takes a minimum of n cycles (one per remap) On processors with no hardware support for the EVR concept, this is not an issue since remaps do not appear in the generated code. The paper by Rau et.al. [17] describes how to generate code for such processors by using kernel unrolling and variable renaming. For processors that do support the EVR concept in hardware, we have two options. The first option is to generalize the concept of the remap operation so that a single operation can perform remap by ....
B. R. Rau, M. S. Schlansker, and P. P. Tirumalai. Code Generation Schemas for Modulo Scheduled DO-Loops and WHILE-Loops. Proceedings of the 25th Annual International Symposium on Microarchitecture (Portland, Oregon, 1992), 158-169.
Loop Optimization Techniques On Multi-Issue Architectures - Kaiser (Correct)
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B. R. Rau, e. al., Code Generation Schema for Modulo Scheduled DO-Loops and WHILE-Loops, Hewlett-Packard Laboratories, Technical Report HPL-92-47, 180 1992.
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