W. L. Lynch, G. Lauterbach, and J. I. Chamdani. Low load latency through sum-addressed memory (sam). In 25th Annual International Symposium on Computer Architecture, pages 369--379, 1998. Home/Search Document Not in Database Summary Related Articles Check |
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Exploiting Partial Operand Knowledge - Brian Mestan University (Correct)
....matching as a technique for allowing a cache access to be done in par allel with address generation by utilizing partial address bits. Sum addressed caches take a different approach to reducing the load to use latency by performing the address calculation (base offse0 in the cache array decoder [15]. Partial tag matching and sum addressed indexing are orthogonal, in that both techniques could be combined as they target separate areas of the level 1 cache access. Figure 7 characterizes the number of bits of a cache tag needed in a set associative cache to either find a unique member that ....
W.L. Lynch, G. Lauterbach, J. I. Chamdani. Low Load Latency Through Sum-Addressed Memory (SAM), In Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998.
Using Internal Redundant Representations and Limited Bypass to.. - Brown, Patt (2001) (1 citation) (Correct)
....binary adder. Section 3.4 discusses the delays of redundant binary adders relative to carry lookahead adders. Section 3.5 describes overflow in the redundant binary system and detection of 2 s complement overflow. These sections are primarily a review of information presented in previous work [2, 3, 9, 11, 16]. Section 3.6 describes how other operations used in a modern instruction set, specifically the Alpha ISA, may be handled in a redundant binary system. 3.1. Overview Most current ISAs use 2 s complement representation for integers. Two s complement representation has several attractive ....
....a one hot vector of word lines. The one hot vector is produced using a separate equality test for each word line rather than a full carry propagating addition. The Sun UltraSPARC III uses Sum Addressed Memory to avoid the base displacement calculation normally needed for address computation [11]. SAM can be used to index the data cache with a single redundant binary number by treating the positive and negative components of the number as the two SAM inputs. It is also possible to use a modification of SAM to eliminate the base displacement calculation when the base register is in ....
W. L. Lynch, G. Lauterbach, and J. I. Chamdani. Low load latency through sum-addressed memory (SAM). In Proc. of ISCA-25, pages 369 -- 379, 1998.
A Permutation-based Page Interleaving Scheme to Reduce.. - Zhang, Zhu, Zhang (2000) (4 citations) (Correct)
....overhead involved is negligible compared with effective reductions of memory stall times. For example, when using the permutation based page interleaving scheme, the average memory access latency of the workloads is around 50 CPU cycles, while the exclusiveOR operation only takes about one cycle [11]. Using memory access scheduling techniques to exploit row buffer locality and concurrency is another attractive approach (e.g. 16] We believe the combination of access scheduling and the permutation based interleaving scheme can further improve memory performance. Acknowledgment: We ....
W. L. Lynch, G. Lauterbach, and J. I. Chamdani. Low load latency through sum-addressed memory (SAM). In Proc. of the 25th Annual International Symposium on Computer Architecture, pages 369--379, 1998.
Cache Implications of Aggressively Pipelined High.. - Dysart, Moore.. (Correct)
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W. L. Lynch, G. Lauterbach, and J. I. Chamdani. Low load latency through sum-addressed memory (sam). In 25th Annual International Symposium on Computer Architecture, pages 369--379, 1998.
Memory Dependence Prediction - Andreas Ioannis Moshovos (Correct)
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W. L. Lynch, G. Lauterbach, and J. I. Chamdani. Low Load Latency through Sum-Addressed Memory (SAM). In Proc. ISCA-25, June 1998.
Direct Load: Dependence-Linked Dataflow Resolution of.. - Chung, Zhang, Peir.. (Correct)
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W. Lynch, G. Lauterbach and J. Chamdani, \Low Load Latency through Sum-Addressed Memory (SAM)," Proc. of 25th Annual Int'l Symp. on Computer Architecture, Barcelona, Spain, June 1998, pp. 369-379.
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