Intel Corporation. The IA-32 Architecture Software Developer's Manual, Volume 1: Basic Architecture. Intel Corporation, Jan. 2002. Available at http://www.intel.com/design/pentium4/manuals/ 24547010.pdf. Home/Search Document Not in Database Summary Related Articles Check |
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Enhancing Loop Buffering of Media and Telecommunications.. - Sias, Hunter, Hwu (2001) (2 citations) (Correct)
.... In general purpose, VLIW styled architectures such as Intel s Itanium, on the other hand, full predicated execution support (a predicate register file, predicate defining operations, and a guard predicate operand on each operation) allows the compiler to implement general control without branches [6]. Such an approach, however, is considered impractical in embedded processors because of the encoding cost of the guard operands (operations on Itanium are 41 bits in length) Media and telecommunications processors therefore typically incorporate a form of partial predication, the addition of a ....
....of a new register file, the addition of new bypass logic for predicate values, the modification of existing bypass logic to allow squashing of nullified operations, and, perhaps most costly, the addition to each operation of a guard predicate operand. The IMPACT model, like the Itanium model [6], consumes 41 bits per operation today unacceptable in an embedded domain. Bits in embedded operation encodings are at a premium, as memory size is limited and ILP techniques critical to performance in media applications need many registers to express enough parallelism for wide issue cores. ....
Intel Corporation, IA-64 Architecture Software Developer's Manual, revision 1.1, July 2000.
Enhancing the Move framework: Endianness port and Immediates.. - Janssen (Correct)
....in which two slots together form a 60 bit immediate suitable for e.g. address displacements in a relative branch. A so called template of 5 bits at the beginning of the instruction word contains, amongst other information, information on what kind of instructions the various slots contain [Int00]. Note that you will see that the solution for immediates in the MOVE framework resembles the solution that the developers of the IA 64 architecture came up with. Figure 5.2 shows a sample of IA 64 instruction format. The template t specifies what kind of instructions each slot contains. The ....
Intel Corporation. The IA-64 Architecture Software Developer's Manual, July 2000. Volume 3, rev 1.1, Instruction set reference.
Parallel Processor Scheduling with Delay Constraints - Engels, Feldman, Karger, Ruhl (2001) (5 citations) (Correct)
....the instructions for the individual functional units into one single instruction word, hence the name VLIW. The VLIW architecture is the basis for Intel s Itanium chip (formerly code named Merced) which is scheduled for commercial release in 2000. It uses a new instruction set named IA 64 [9], which was developed by Intel and Hewlett Packard, and is based on EPIC (Explicitly Parallel Instruction Computing) Intel s adaptation of VLIW. VLIW architectures have also been used in state of the art Digital 1 When we say that the precedence graph is a forest, we mean that it is either a ....
Intel Corporation. The IA-64 Architecture Software Developer 's Manual, January 2000.
Cycles to Recycle: Garbage Collection on the IA-64 - Hudson, Moss, Subramoney, al. (2000) (2 citations) (Correct)
....topic. We close with further discussion of the most significant features in light of the more detailed GC implementation topics. 2. FEATURES OF THE IA 64 ISA Here is a description of the aspects of the IA 64 relevant to memory management. A reference work is available for the interested reader [9]. Data types: The IA 64 directly manipulates 8, 16, 32, and 64 bit signed and unsigned integer quantities, as well as floating point numbers, etc. General registers (GR) There are 128 general purpose 64 bit registers. GR0 is hard wired to the value 0. There is a separate file of 128 floating ....
Intel Corporation. The IA-64 Architecture: Software Developer's Manual. Santa Clara, CA, Jan. 2000. URL: http://developer.intel.com/design/ia-64/manuals/.
ILP-based Instruction Scheduling for IA-64 - Kästner, Winkel (2001) (2 citations) Self-citation (Ia) (Correct)
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Intel, http://www.intel.com/ia64, IA-64 Architecture Software Developer's Manual, Volume 1: IA-64 Application Architecture, Revision 1.1, July 2000.
Improving the Reliability of Commodity Operating Systems - Swift, Bershad, Levy (2003) (12 citations) (Correct)
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Intel Corporation. The IA-32 Architecture Software Developer's Manual, Volume 1: Basic Architecture. Intel Corporation, Jan. 2002. Available at http://www.intel.com/design/pentium4/manuals/ 24547010.pdf.
Peppermint and Sled: Tools for Evaluating SMP Systems .. - Basu, Roy, Kumar.. (2002) (Correct)
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intel. Intel R #IA-64 Architecture Software Developer's Manual, volume 4, chapter Processor Performance Monitoring. Intel Corporation, 1.1 edition, July 2000.
A Survey on the Interaction between Caching, Translation and.. - Wiggins (2003) (Correct)
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Intel Corp. IA-32 Architecture Software Developer's Manual, 2002. URL http://developer.intel.com/design/pentium4/manuals.
Reconstructing Control Flow from Predicated Assembly Code - Decker, Kästner (2003) (Correct)
No context found.
Intel, IA-64 Architecture Software Developer's Manual, Volume 1: IA-64 Application Architecture, Revision 1.1, July 2000.
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