L. Carloni, K. McMillan, A. Saldanha, A. Sangiovanni-Vincentelli, "A Methodology for Correct-by-Construction Latency Insensitive Design", ICCAD'99.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....between systems. This paper addresses both of these issues. First, two basic mixed timing FIFO s are introduced which address the first design challenge, for both sync sync and async sync interfaces. For the second design challenge, latency insensitive protocols were proposed by Carloni et al. [2]; however, their solution was limited to a single clock domain. In this paper, their solution is generalized to mixed timing systems: two new mixed timing relay stations are introduced (syncsync, async sync) which built on our basic designs. A particular contribution of this paper are the new ....

....Work. A number of papers propose FIFO s and components to handle timing discrepancies between subsystems. Some designs are limited to handling single clock systems. These approaches have been proposed to handle clock skew [10, 11] drift and jitter [10] and very long interconnect penalties [2]. Several designs have also been proposed to handle mixed timing domains. One category of approaches attempts to synchronize data items and or control signals with the receiver, without interfering with its clock ( 12, 13] In particular, Seizovic [13] robustly interfaces asynchronous with ....

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L. Carloni, K. McMillan, A. Saldanha, A. Sangiovanni-Vincentelli, "A Methodology for Correct-by-Construction Latency Insensitive Design", ICCAD'99.

....proposed interconnect scheme allows any resource to reach any other resource, an overhead, we believe, is justified. Performance overhead. A more concrete answer than the area overhead can be given here. Interconnect delay already dominate the performance equation and Luca Carloni et al. see [2]) have proposed a delay insensitive design, which essentially involves pipelining the wires and adding logic to the functional computational blocks to implement the pipeline control. According to ITRP99 by the time we reach .1 micron, the delay in long wires would be 100x compared to the fastest ....

....blocks. This observation leads to three conclusions. The first is, if the delay in wire is going to be 100x compared to a gate and if switches imply a small depth of gates, the switches would add an insifnificant amount of delay. Secondly, if as proposed by Luca Carloni et al. see [2]) delay insensitive design style involving pipelining the wire, is essential for present and future technology, the overhead of switching is comprable to that of the overhead of delay insensitive design style. Lastly, maintaining global synchronous assumption is already proving to be difficult ....

Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli. A Methodology for Correct-by-Construction Latency Insensitive Design. Proceedings of ICCAD 1999. San Jose, USA.

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