Balarin, F., Chiodo, M., Giusto, P., Hsieh, H., Jurecska, A., Lavagno, L., Sangiovanni-Vincentelli, A., Sentovich, E. M., and Suzuki, K. (1999). Synthesis of software programs for embedded control applications, IEEE Trans. CAD, 18(6), 834--849. Home/Search Document Details and Download
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System Modeling and Design Refinement in ForSyDe - Sander (2003) (Correct)
....mathematical framework and are excellently suited for their application areas, e.g. digital signal processing applications, they do not have an abstract notion of time and thus cannot be used to express timing properties and constraints on a level that abstracts from physical time. Balarin et al. [7] argue, that the synchronous assumption, though very convenient from the analyzing point of view, imposes a too strong restriction on the implementation, as it has to be fast enough . They advocate a GALS (globally asynchronous locally synchronous) approach and implement it in the POLIS ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(6):834-- 849, June 1999.
Optimization and Synthesis for Complex Reactive Embedded Systems.. - Chiodo (2002) (Correct)
....will be faster and will use less data memory than an equivalent multi step implementation but will use more code memory. A multi step implementation may be desirable if it allows to fit the program in the amount of memory available while maintaining acceptable performance. 2. RELATED WORK In [4, 5] a software synthesis methodology is proposed that operates on an extended FSM model called codesign FSM (CFSM) 9] which extends classical FSMs with arithmetic and relational operators. Structurally, A CFSM is a directed network of one combinational control node (CTR) one or more combinational ....
....Within each group of CTRs that share the same BDD manager (called a region) the composition of CTRs is done incrementally in pairs. In order to avoid the BDD explosion, each composition will take place only if the sizes of the BDDs to be combined are below a given set limit. As in [4] and [5], here we make the simplifying assumption that each step in the implementation (as does each BDD node) has the same cost, and that each code path (as does each BDD path) has the same probability of being traversed. Since reducing the size of the BDD reduces its average depth, we only consider the ....
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F.Balarin et al. Synthesis of software programs for embedded control applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(6):834--849, June 1999.
Transformation Based Communication and Clock Domain.. - Sander, Jantsch (2002) (Correct)
....small variety of concepts and methods based on deep, elegant, but simple mathematical principles [2] The synchronous assumption implies a total order of events and leads to a clean separation between computation and communication and gives a solid base for formal methods. Balarin et al. [1] argue, that the synchronous assumption, though very convenient from the analyzing point of view, imposes a too strong restriction on the implementation, as it has to be fast enough . They advocate a GALS (globally asynchronous locally synchronous) approach and implement it in their methodology ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Transactions on 18(6):834--849, June 1999.
Software Synthesis from Synchronous Specifications Using.. - Jiang, Brayton (2002) (9 citations) (Correct)
....experimental results followed by conclusions. 2. RELATED WORK The Polis project [2] uses EFSMs for intermediate representation and synthesis. A high level design language, like Esterel [7] is compiled into a set of EFSMs, which are subsequently optimized and mapped into hardware and or software [3], depending on system constraints. The communication model among these EFSMs is a Globally Asynchronous Locally Synchronous (GALS) mechanism. Each EFSM is represented by a single state transition table for the control path and a lookup table for the data path. Binary Decision Diagrams (BDDs) are ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. L. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Trans. Comput.-Aided Design Integrated Circuits, 18(6):834--49, June 1999.
Comparison of Decision Diagrams for Multiple-Output Logic.. - Sasao, IGUCHI, MATSUURA (2002) (Correct)
....for non zero outputs) is introduced. In this paper, we show that by using BDDs for ECFNs, logic evaluation can be more than two times faster than by using SBDDs. Also, the size of the memory is smaller than by using SBDDs. This method can be useful for logic simulation [1, 3] and embedded system [2]. 2 Function Evaluation using BDDs Another method to represent a logic function is the branching program. Fig. 2.1 shows a method to convert a BDD into a branching program. For a given logic function, construct a binary decision diagram (BDD) as shown in Fig. 2.1(a) Then, replace each ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embed-ded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp. 834-849, June 1999.
Representations of Logic Functions using QRMDDs - Nagayama, Sasao, Iguchi.. (2002) (Correct)
....functions show that the area time complexity takes its minimum when # is between # and #. 1. Introduction With the increase of the complexity of digital systems, representations of logic functions that can evaluate functions efficiently and require small amount of memory are becoming important [2]. In this paper, we consider representations of two valued logic functions using quasi reduced multi valued decision diagrams with # bits (QRMDD(#)s) As for methods to represent logic functions by decision diagrams (DDs) binary decision diagrams (BDDs) 1, 7] and multi valued decision diagrams ....
....evaluate it. The measure ## is used when both the amount of memory and the number of memory accesses are equally important. On the other hand, the measure ## is used when the number of memory accesses is more important than the amount of memory. For example, ## can be used for embedded systems [2], while ## can be used for logic simulators [8, 9] 4.4 Experimental Results For each benchmark function in Table 2.1, we obtained three measures #, ## , and ## . Table 4.1, Table 4.2, and Table 4.3 show the relation of # and #, ## , and ## , respectively. In these tables, ### denotes ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
Compact BDD Representations for Multiple-Output.. - Sasao, MATSUURA.. (2001) (Correct)
....exists that requires and # nodes in BDDs for the ECFN with the encoding optimized and un optimized, respectively. 3 Application to Embedded Systems 3. 1 Branching Program Here, we consider the application to embedded systems, where the size of the memory is very important [3]. The branching program method realizes a logic function by a sequential network as follows: 1) Represent the given logic function by a BDD [4] Fig. 3.1(a) where dotted lines show 0 edges and solid line show 1 edges) 0 1 v 0 v 1 v 2 x 1 x 2 x 3 v 3 v 4 (a) if( goto ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
An Esterel Compiler for Large Control-Dominated Systems - Edwards (2002) (3 citations) (Correct)
....and leaves that set the next state. Automata compilers produce very fast code, but it can be exponentially larger than the source program since they generate separate code for each possible state of the program. Two approaches has been proposed to reduce this code size. The Polis group s [5] [6] automata compiler uses a binary decision diagram to identify code that can be shared between states. Castelluccia, Dabbous, and O Malley [7] also share subtrees to reduce code size, but also attempt to improve code speed by inlining called functions, swapping then and else branches to improve ....
....that is evaluated when the node runs. If the node has two or more successors, the result of the expression is used to choose among them. A code generation algorithm could simply generate the code for each node and use goto statements to branch to the appropriate location. The Polis compiler [5] [6] does this and the results, while correct, are inscrutable, although this is partly due to the unstructured control graphs generated from BDDs. Structuring control flow graphs has been studied in a few contexts. Baker [14] proposed an algorithm for finding highlevel control constructs (e.g. ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Transactions on Computer-Aided Design, vol. 18, pp. 834--849, June 1999.
Bi-Partition of Shared Binary Decision Diagrams - Matsuura, Sasao, Butler, Iguchi (2001) (Correct)
....of partitioned SBDDs are similar to that of partitioned BDDs and FBDDs. 1) Hardware synthesis. Replace each non terminal node of an SBDD by a multiplexer (MUX) forming a network for . This is used to design multiplexer type FPGAs [4] and pass transistor logic [23] 2) Software synthesis [2, 19]. Replace each non terminal node by an if then else statement, forming a branching program for . 3) Verification [13, 14, 6] In verification, a monolithic 0 1 0 1 f = x 1 x 2 x 3 x 4 0 f = x 1 x 2 x 3 x 4 1 v x 1 x 2 x 3 x 4 (a) Before sharing (14 nodes) 0 1 f 0 f 1 x 1 x 2 x 3 x 4 ....
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
J. of Mult.-Valued Logic Soft Computing., Vol. 11, pp.. - Old City Publishing (Correct)
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Balarin, F., Chiodo, M., Giusto, P., Hsieh, H., Jurecska, A., Lavagno, L., Sangiovanni-Vincentelli, A., Sentovich, E. M., and Suzuki, K. (1999). Synthesis of software programs for embedded control applications, IEEE Trans. CAD, 18(6), 834--849.
On the Optimization of Heterogeneous MDDs - Nagayama, Sasao (2005) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 6, pp. 834--849, Jun. 1999.
Optimizations For Faster Execution Of Esterel Programs - Potop-Butucaru, de Simone (2004) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Transactions on Computer-Aided Design, 18(6):834--849, 1999.
On the Minimization of Longest Path Length for Decision Diagrams - Nagayama, Sasao (2004) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
Area-Time Complexities of Multi-Valued Decision Diagrams - NAGAYAMA, SASAO, IGUCHI.. (2004) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E.M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.18, no.6, pp.834--849, June 1999.
Compact Representations of Logic Functions Using Heterogeneous .. - Nagayama, Sasao (2003) (Correct)
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F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
Software Technology - Unu-Iist Report No (Correct)
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Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Lukiano Lavagno, Alberto Sangiovanni-Vincentelli, Ellen M. Sentovich, and Kei Suzuki. Synthesis of Software Programs for Embedded Control Applications. IEEE Transactions on Computeradded Design of Integrated Circuits and Systems, 18(6):834-848, June 1999.
Evaluation of Multiple-Output Logic Functions using.. - Yukihiro Iguchi Tsutomu (2003) (1 citation) (Correct)
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F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embed-ded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp. 834-849, June 1999.
RePIC - A New Processor Architecture Supporting.. - Chow, Tong.. (1985) (3 citations) (Correct)
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F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 834-849, 1999.
Compact Representations of Logic Functions Using Heterogeneous .. - Nagayama, Sasao (2003) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E.M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.18, no.6, pp.834--849, June 1999.
On the Minimization of Average Path Lengths for Heterogeneous.. - Nagayama, Sasao (2004) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
Code Generation for Embedded Systems Using Heterogeneous MDDs - Shinobu Nagayama Tsutomu (2003) (Correct)
No context found.
F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. CAD, Vol. 18, No. 6, pp.834-849, June 1999.
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