S. Hily and A. Seznec. Standard memory hierarchy does not fit simultaneous multithreading. In Workshop on Multithreaded Execution Architecture and Compilation, Jan. 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....not investigated, and that paper gives no indication that a similar technique is necessary for loads. Previous work on the interaction of SMT processors and the cache hierarchy have focused on cache size and organization (Nemirovsky and Yamamoto [11] cache bandwidth limitations (Hily and Seznec [6]) or cache partitioning [18] Cache prefetching [3, 10] attacks the long latency load problem in a different way, seeking to eliminate the latency itself. Recent work in prefetching targets multithreaded processors specifically, using idle hardware contexts to initiate prefetching. These include ....

S. Hily and A. Seznec. Standard memory hierarchy does not fit simultaneous multithreading. In Workshop on Multithreaded Execution Architecture and Compilation, Jan. 1998.

....As in [1] Nemirowsky and 2 Yamamoto show that by increasing cache capacity and associativity, the overall miss ratio decreases. Furthermore, by increasing line size, the miss ratio decreases for large capacities but increases for small capacities due to extrinsic misses. S. Hily and A. Seznec [3] investigate the memory hierarchy in simultaneous multithreaded processors [4] 5] They study the relationship between the number of supported threads and the cache size, associativity and block sizes and its impact on the miss ratio. They also show that ignoring L2 cache contention can result in ....

....to interferences among the threads that share the processor. We can observe that, as the number of threads increases, the contribution of the interthreads miss ratio to the overall miss ratio also increases. The conclusions we can draw from these results are similar to those of other studies [1] 2][3]: associative caches reduce the miss ratio much more significantly in 4 threads than in one thread. When the number of threads sharing the processor increases, the likelihood of having references from different threads colliding in a cache line (ping pong effect) is higher, and so, the percentage ....

S. Hily and A. Seznec "Standard Memory Hierarchy Does Not Fit Simultaneous Multithreading", in Proc. of the Workshop on Multithreaded Execution Architecture and Compilation (with HPCA-4). January 1998

....As in [1] Nemirowsky and Yamamoto show that by increasing cache capacity and associativity, the overall miss ratio decreases. Furthermore, by increasing line size, the miss ratio decreases for large capacities but increases for small capacities due to extrinsic misses. S. Hily and A. Seznec [3] also investigate the memory hierarchy in simultaneous multithreaded processors [4] 5] They study the relationship between the number of supported threads and the cache size, associativity and block sizes and its impact on the miss ratio. S. Hily and A. Seznec also show that ignoring L2 cache ....

....the threads that are sharing the processor. We can observe that, as the number of threads increases, the contribution of the inter threads miss ratio to the overall miss ratio also increases. The conclusions we can extract from these results are similar to those pointed out in previous works [1] 2][3]: associative caches cause a reduction in the miss ratio that is much more significant for 4 threads than for one thread. When the number of threads sharing the processor increases, the likelihood of having references from different threads colliding in a cache line (ping pong effect) is higher, ....

S. Hily and A. Seznec "Standard Memory Hierarchy Does Not Fit Simultaneous Multithreading", in Proc. of the Workshop on Multithreaded Execution Architecture and Compilation (with HPCA-4). January 1998

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC