M. C. McFarland, "Formal verification of sequential hardware: A tutorial," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 633--653, May 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....early stages of the VLSI design flow shown in Figure 1.1: verification and testing. Verification involves comparing the implementation to the initial specification. If there are mismatches during verification, then the implementation may need to be modified to more closely match the specification [128]. In traditional VLSI design flow the comparison between specification and implementation is accomplished through exhaustive simulation. Because exhaustive simulation for complex designs is practically infeasible, simulation provides at best only a probabilistic assurance. Formal verification, in ....

M.C. McFarland. Formal verification of sequential hardware: A tutorial. IEEE 12(5):633--654, May 1993.

....signals ue k round robin (table 1) one gets a sequential machine. In the following, we assume that this sequential machine behaves as desired. It will serve as a reference for the correctness proof. However, there is a vast amount of literature on formally verifying sequential machines, e.g. [16, 25]. 3. ADDING A STALL ENGINE In order to realize interlock, we need means to stall the execution in certain stages while the execution proceeds in the stages below. Thus, as first step of the transformation into a pipelined machine, we add a stall engine. A stall engine is a module that takes a set ....

M. McFarland. Formal verification of sequential hardware: A tutorial. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(5):633--654, 1993.

....analysis to modify some functionality of the behavioral model to further illustrate the effectiveness of our generated sequence. Simulation results show that all 54 mutants in the branch prediction functionality can be detected by measuring transition coverage. 1 Introduction Formal verification [1, 2, 3, 4, 5] has been the focus of many current approaches to detect design errors. It provides a rigorous means to prove the correctness of a design by establishing that a mathematical relation holds between two descriptions of a system. A less rigorous but more practical approach to ensuring correctness ....

M. C. McFarland. "Formal Verification of Sequential Hardware: A Tutorial," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 5, pp. 633--654, May 1993.

....to the PowerPC 604 superscalar microprocessor. The experimental results are presented in Section 6. Summary and conclusion are documented in Section 7. 2 Related Work An alternative to the current practice of design validation via simulation is the use of formal methods for design verification [9, 10, 22, 23, 32]. Design verification techniques have proven to be quite successful in verifying logic circuits. More recently these techniques have been extended to verifying microprocessors. However, only a portion of a complex microprocessor or relatively simple microprocessors can be verified using these ....

M. C. McFarland. "Formal Verification of Sequential Hardware: A Tutorial,". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 5, pp. 633--654, May 1993.

.... for specifications of a microelectronic system [DC92] The formalization of the specification process has a counterpart in the design process [TB93] Indeed, the capability to use of formal methods to verify a hardware design is an important side effect of a formally specified part of a system [McF93b, CP88] Formal verification methods for large systems are still in primitive stages, but the formal verification of subsystems (e.g. a digital FSM or a floating point unit) are within the capabilities of present day commercial tools. System Application Level of Abstraction Estelle Formal ....

M. C. McFarland. Formal Verification of Sequential Hardware: A Tutorial. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(5):633--654, May 1993.

....cannot be executed in a procedural way 1 . This situation should be clearly improved upon. The problem of formal verification of design steps was addressed by many researchers. Up to now, verification techniques have mainly concentrated on the circuit, logic and architectural RT level [1, 2, 11]. These are important and complementary to our approach but they are not sufficient to apply directly on our problem. The optimized code is structured in a completely different way with global loop modifications. When all this code would be unrolled this would lead to hundreds of thousands of ....

....loop related) ordering of operations in the specification is not changed during the synthesis [6, 18] This is not acceptable in our application domain where this modification is a major source of optimization, as already indicated. Another approach is based on a correctness preserving methodology [11, 12]. With this approach a correct design can be obtained, but designers are limited in the modeling power and in the number of transformations available. This usually restricts the design flexibility. Moreover, only small transformations steps are possible and the approach does not allow to verify ....

M.C.McFarland, Formal verification of sequential hardware: a tutorial, IEEE Trans. on Comp.-aided Design, Vol.12, No.5, pp.633-654, May 1993.

....[18] A model at the system level should be expressed in a form that enables verification that a refinement correctly implements the model. Possible approaches include behavioural synthesis [32] correct by construction) and formal verification using model checking and equivalence checking [23, 33]. Refinement to a software implementation is facilitated by a system level modeling language that is closely related to programming languages. In principle, the hardware and software implementations could be expressed in the same language as the system level model, thus avoiding semantic ....

M. C. McFarland, "Formal Verification of Sequential Hardware: A Tutorial," IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 12, no. 5, pp. 633--654, 1993.

....of hardware systems in general more tractable than more general systems. A survey of the large number of different hardware verification techniques which have been proposed is beyond the scope of this paper (an introduction to the topic and a good set of references to the topic can be found in (McFarland, 1993)) The work presented here draws on three techniques. 1. Theorem proving: Theorem provers are based on formal systems such as logic. For hardware verification, both the specification and implementation can be described in logic, and the task of verifying the system is to prove that the ....

McFarland, Michael C. 1993. Formal Verification of Sequential Hardware: A Tutorial. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(5), 633--654.

....This chapter is intended to place the thesis work in perspective and relate the research to other work. It is not intended as a comprehensive survey of verification, and therefore some simplifications are made and important verification methods skimmed over. For fuller surveys on the topic see [73, 97, 119]. Overview of Chapter Section 2.1 briefly introduces a method of representing boolean functions. Since boolean expressions are used extensively in verification for a variety of purposes, efficient methods for representing and manipulating them is essential. The review of verification starts with ....

M.C. McFarland. Formal Verification of Sequential Hardware: A Tutorial. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(5):633--654, May 1993.

....A A 0 , then LA (N) L A 0 (N 0 )dA if and only if L A 0 [A (N 0 k N)dA = LA (N ) The proof of this equivalence follows from the the argument in [39] about the properties the weaving of trace structures. This approach is similar to those used for finite state machine verification [25]. It should be noted that we do not yet specify inputs and outputs between the circuit and its environment. Their communication is thus undirected and amounts to pure (rendez vous type) synchronisation, which is conveniently used to define the control flow at the initial stage. The specifications ....

M.C. McFarland. Formal verification of sequential hardware: a tutorial. IEEE Trans. CAD of integrated circuits and systems, 12(5), May 1993.

....to process the tremendous amount of input data is prohibitive (thus forbidding an exhaustive verification) Speeding up simulation by using hardware accelerators and modellers (when available) is still (by an order of magnitude) below the required throughput. 2. Formal verification methods [3] provide the designer with properties that hold for all possible design behaviors by proving that a mathematical relation between the design implementation and its specification is true. Theorem proving consists in verifying that the implementation is equivalent to (or implies) the specification. ....

Michael, C. McFarland. Formal verification of sequential hardware : A tutorial. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(5):633--654, 1993.

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M. C. McFarland, "Formal verification of sequential hardware: A tutorial," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 633--653, May 1993.

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M. C. McFarland. Formal verification of sequential hardware: A tutorial. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(5):633 -- 654, May 1993.

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M.C.McFarland, "Formal verification of sequential hardware: a tutorial", IEEE Trans. on Comp.-aided Design, Vol.12, No.5, pp.633-654, May 1993.

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