F. N. Najm, "A Survey of Power Estimation Techniques in VLSI Circuits," IEEE Transactions on VLSI Systems, Vol. 2, No. 4, pp. 446-455, 1994. Home/Search Document Details and Download
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....path. Then, the path function is given by If there are paths between and , then the total path function is given by The path probability , the probability that at the end of the cycle, the path from to is conducting, follows from elementary probability theory or binary decision diagram analysis [23]. The source and drain conditional probabilities required for the detailed body voltage estimation are given by specific path probabilities. For example, is the path probability between the drain node and with the gate of the target transistor low. We next consider calculating the FET arrival ....
F. N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. VLSI Syst., vol. 2, pp. 446--455, Dec. 1994.
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....etc. On an average, the estimates of the switching capacitance are within 12 of the actual switching capacitance measured by simulating the switch level models from the layouts. 2 Previous Work Power estimation techniques at the gate and lower levels of abstraction can be broadly classified [1] into (1) simulation based techniques; 2) probabilistic techniques; and (3) statistical techniques. Typically, in a simulation based technique [2, 3, 4] the average power is calculated by monitoring either the supply voltage or current waveforms or both. These are too slow to handle very large ....
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.... activity values can be computed considering complete logic and routing delays (routed delay activity) Various approaches to computing switching activity have been proposed in the literature, and they can generally be classified as either simulation based approaches or as probabilistic approaches [9, 14]. When delays are considered, switching activity normally increases due to the introduction of glitches, which are spurious logic transitions on a net caused by unequal path delays to the net s driving gate. As transitions on gate inputs occur at di#erent times, the net experiences multiple ....
F. Najm. A survey of power estimation techniques in VLSI circuits. IEEE Trans. on VLSI Systems, 2(4):446--455, December 1994.
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