J. White, S. Devadas, and K. Keutzer, "Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation," IEEE Transactions on Computer-Aided Design, pp. 377-383, March 1992.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....maximum power estimation problem. I.2 The maximum power for given transition joint transition probability specification for the circuit inputs. We refer to this as the constrained maximum power estimation problem. A number of techniques have been developed to solve the problems in Category I. 1 [1] [10] Category I.2 has however not been explored. The method proposed in [1] propagates the signal uncertainty through the circuits to obtain a loose upper bound on the maximum power. The bound is then made tighter by doing analysis of the circuit structure. The bound tightening method tends to ....

....probability specification for the circuit inputs. We refer to this as the constrained maximum power estimation problem. A number of techniques have been developed to solve the problems in Category I.1 [1] 10] Category I.2 has however not been explored. The method proposed in [1] propagates the signal uncertainty through the circuits to obtain a loose upper bound on the maximum power. The bound is then made tighter by doing analysis of the circuit structure. The bound tightening method tends to be time consuming when the number of the primary inputs is large. Automatic ....

[Article contains additional citation context not shown here]

S. Devadas, K. Keutzer, and J. White. "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation", IEEE Transactions on ComputerAided Design, 11(3):373-383, March 1992.

.... on the kind of gate input and output activity, including an important contribution due to glitches [15] Nevertheless, it is important to notice that several simulation based (at either the logic [16, 17, 18] or the electrical level [19] or pattern independent (probabilistic [20, 21] or symbolic [22]) techniques can be used to evaluate P gate and, therefore, P active once the kind of input activityatC is known. Since the only differences between the standard and the proposed implementation is due to the presence of the two additional power supplies, it is reasonable to suppose P active ....

S. Devadas, K. Keutzer, and J. White, "Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation," IEEE Transaction on CAD,vol. 11, no. 3, pp. 373 -- 383, 1992.

....probably be lower. To further improve the sleep transistor reduction, we can also use more rigorous criteria to determine mutual exclusivity that is based on logic rather than the structural connections in a circuit. We are currently working on such an approach that utilizes boolean manipulation[7]. g 1 g 2 g 3 g 4 g 5 g 6 g 8 g 7 g 9 g 10 1 1 1 2 2 3 4 2,3 (3,4) 7 3, 4,5) 9 Figure 5. Logic gates annotated with all possible transition times, so that sleep resistors can be merged. Grouping #1 = g 1 , g 4 , g 6 , g 8 Grouping #2 = g 2 , g 7 , g 9 Grouping #3 = g ....

S. Devadas, K. Keutzer, J. White, "Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation," IEEE JSSC, vol. 11, no. 3, pp. 373-383, March 1992.

....statistical techniques and deterministic techniques. In statististical techniques [6] the maximum power consumption is estimated using order statistics derived from a simple randomsample. In deterministic techniques, the maximumpower is estimated either by solving the max satisfiability problem [7] or by using approximation techniques [8, 7, 9] to obtain an upperbound on the maximum power consumption. The disadvantage of the statistical technique is that the size of the sample can be high and therefore it may require large simulation times. The disadvantage of the # This research was ....

....techniques. In statististical techniques [6] the maximum power consumption is estimated using order statistics derived from a simple randomsample. In deterministic techniques, the maximumpower is estimated either by solving the max satisfiability problem [7] or by using approximation techniques [8, 7, 9] to obtain an upperbound on the maximum power consumption. The disadvantage of the statistical technique is that the size of the sample can be high and therefore it may require large simulation times. The disadvantage of the # This research was supported in part by DARPA under contract no. ....

S. Devadas, K. Keutzer, and J. White. Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(3):373--383, March 1992.

....small time interval. Therefore, accurate circuit timing (gate and interconnection delays) should be considered during the process of the maximum current estimation. Several research groups have worked on estimating the maximum instantaneous current through the power supply lines of CMOS circuits [1,4,6,10,14,15]. Methodologies proposed in [1,4] are applicable only to small circuits. They produce a lower bound on the maximum instantaneous current through the power and ground lines. Kriplani et al. 10] present a pattern independent algorithm to find an upper bound on the maximum current. However, because ....

....timing (gate and interconnection delays) should be considered during the process of the maximum current estimation. Several research groups have worked on estimating the maximum instantaneous current through the power supply lines of CMOS circuits [1,4,6,10,14,15] Methodologies proposed in [1,4] are applicable only to small circuits. They produce a lower bound on the maximum instantaneous current through the power and ground lines. Kriplani et al. 10] present a pattern independent algorithm to find an upper bound on the maximum current. However, because of their assumption that all ....

[Article contains additional citation context not shown here]

S. Devadas, K. Keutzer, and J. White, "Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation," IEEE Transactions on CAD, pp. 373-383, March 1992.

....practical way to solve the problem is to generate a tight lower bound and an upper bound for maximum power consumption such that the range between lower and upper bound is as narrow as possible. Several approaches have been proposed to estimate the maximum power consumption for CMOS circuits. In [4], Devadas et al. formulated the power dissipation of CMOS circuits as a Boolean function in term of the primary inputs. They tried to maximize the function by solving a weighted max satisfiability problem. During the branchand bound process which maximizes the objective function, the lower bound ....

S.Devadas, K.Keutzer and J.White, "Estimation of Power Dissipation in CMOS Combinational Circuits," IEEE Custom Integrated Circuits Conf., pp. 19.7.1-19.7.6, 1990.

....can be used to further reduce power dissipation. However, our result show that selecting such vectors is computationally very difficult. Experimental evaluation of the proposed algorithms and techniques are presented. Two measures of power dissipation, viz. worst case (or peak) power dissipation[9, 10, 11] and average power dissipation[1, 2] were considered. Power dissipation is a function of the circuit delay. Three delay models have been studied in the literature [9] viz. unit delay, zero delay and general delay. Zero delay gives the least number of transitions while the general delay model ....

....algorithms and techniques are presented. Two measures of power dissipation, viz. worst case (or peak) power dissipation[9, 10, 11] and average power dissipation[1, 2] were considered. Power dissipation is a function of the circuit delay. Three delay models have been studied in the literature [9] viz. unit delay, zero delay and general delay. Zero delay gives the least number of transitions while the general delay model gives the worst case transitions. We present results for the zero delay and the general delay model. Unit delay is a special case of general delay and our algorithms can ....

S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation," IEEE Trans. Computer Aided Design, vol. CAD-11, pp. 373--383, March 1992.

....practical way to solve the problem is to generate a tight lower bound and an upper bound for maximum power consumption such that the range between lower and upper bound is as narrow as possible. Several approachs have been proposed to estimate the maximum power consumption for CMOS circuits. In [4], Devadas et al. formulated the power dissipation of CMOS circuits as a Boolean function in term of the primary inputs. They tried to maximize the function by solving a weighted max satisfiability problem. During the branch and bound process which maximizes the objective function, the lower bound ....

S.Devadas, K.Keutzer and J.White, "Estimation of Power Dissipation in CMOS Combinational Circuits", IEEE Custom Integrated Circuits Conf., pp. 19.7.119. 7.6, 1990.

....consecutive input vectors which maximize the power dissipated by the circuit. Several approaches to estimating the maximum power in a circuit have been proposed in the past. A weighted maxsatisfiability approach, but with a simplified power model, namely weighted output activity, is proposed in [3]. This method tends to overestimate the maximum power consumption. In [5] and [6] an upper bound estimation method for the maximum power is described using the propagation of signal uncertainty waveforms. The approach described, however, does not take into account signal correlations at all in [5] ....

S. Devadas, K. Keutzer and J. White, Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation, IEEE Transactions on Computer-Aided Design, Vol. 11, No. 3, March 1992, pp. 373-383.

....the respective maximum currents were estimated, as the exact maximum estimation problem is NP complete. 4 Previous Work Chowdhury et al. have addressed the problem of maximum current estimation in [5] Devadas et al. have addressed a similar problem of maximum power dissipation estimation in [6]. Both of these works solve the respective NP complete maximum estimation problems by either an exact search technique i.e. a branch and bound algorithm or some heuristic technique. Both of these techniques are based on searching for a specific input pattern that leads to the desired maximum. ....

S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation," IEEE Transactions on Computer-Aided Design, no. 3, pp. 373-- 383, March 1992.

....literals of a logic function is independent of the technology being used to implement the function. This means that the same optimized implementation may be used for static and dynamic logic circuits. The cost functions used for measuring power however are different in static and dynamic circuits[5]. This means that different strategies need to be developed for different technologies. The goal of this paper is to provide function minimization techniques to be used in optimizing power consumption in PLAs. Recent work on minimizing the power consumption of Boolean functions have concentrated ....

S. Devadas, K. Keutzer and J. White. "Estimation of Power Dissipation in CMOS Combinational Circuits using Boolean Manipulations," IEEE Transactions on CAD, vol 11, no 3, March 1992.

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S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits," in Proc. Custom Integrated Circuits Conf., May 1990, pp. 19.7.1--19.7.6.

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S. Devadas, K. Keutzer, and J. White. Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation. IEEE Transactions on Computer-Aided Design, 11(3):373--383, March 1992.

....can be obtained without recourse to time consuming ex haustive simulation. In the )ast, probabilistic peak current estimation methods [e.g. 5] that compute probabilistic current waveforms for combinational circuits have been developed. Estimation of worst case power dissipation (e.g. [10], 7] is a difficult prob lem requiring a branch and bound search and these methods have been applied to small to moderate sized circuits. The problem of estimating average power in combinational circuits can be reduced to one of computing signal probabilities [1] of a multilevel circuit ....

S. Devadas, K. Keutzer, and J. White. Estima- tion of Power Dissipation in CMOS Combinational Circuits. In Proceedings of the Custom Integrated Circuits Conference, pages 19.7.1-19.7.6, May 1990.

No context found.

J. White, S. Devadas, and K. Keutzer, "Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation," IEEE Transactions on Computer-Aided Design, pp. 377-383, March 1992.

No context found.

S. Devadas, K. Keutzer and J. White. " Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. " IEEE Transactions on Computer -Aided Design of Integrated Circuits and Systems, 11(3):373-383, March 1992.

No context found.

S. Devadas, K. Keutzer, and J. White. Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(3):373--383, March 1992.

No context found.

S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation," IEEE Transactions on Computer-Aided Design, 11(3):373-383, Mar. 1992.

No context found.

S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation, " IEEE Transactions on CAD, vol. 11, pp. 373--383, Mar. 1992.

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S. Devadas, K. Keutzer and J. White. " Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. " IEEE Transactions on Computer -Aided Design of Integrated Circuits and Systems, 11(3):373-383, March 1992.

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# S. Devadas, K. Keutzer and J. White, Estimation of Power Dissipation in CMOS Combinational Circuits., Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 19.7.1- 19.7.6, 1990.

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S. Devadas, K. Keutzer and J. White, "Estimation of Power Dissipation in CMOS Combinational Circuits.", Proceedings of the IEEE Custom Integrated Circuits

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S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Trans. Computer-Aided Design, pp. 373--383, Mar. 1992.

No context found.

Devadas, S., Keutzer, K., and White, J. Estimation of power dissipation in CMOS combinational circuits. IEEE Custom Integrated Circuits Conf. (1990). pp. 19.7.1-19.7.6.

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S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Transactions on Computer-Aided Design, vol. 11, no. 3, pp. 373--383, March 1992.

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