Gordon J. Pace, Hardware Design Based on Verilog HDL, Oxford University Computing Laboratory, Programming Research Group. Trinity Term 1998. Home/Search Document Not in Database Summary Related Articles Check |
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Towards an Algebraic Synthesis of Verilog - Iyoda, Jifeng (2001) (1 citation) (Correct)
....of the process is guaranteed by construction, eliminating the functional checking between pre and pos synthesis simulation. This approach characterises the synthesis process as a simple parallelisation of a sequential language. There are several works towards a formalization of Verilog [2, 9, 11, 18]. The algebraic laws used in our synthesis process can be justi ed in terms of the operational semantics of Verilog and the concept of bisimulation [8, 9, 10, 18] This approach addresses a still open question in hardware design [3] This paper is organized as follows. The Section 2 de nes the ....
Gordon J. Pace. Hardware Design Based on Verilog HDL. PhD thesis, University of Oxford, UK, 1998. Oxford University Computing Laboratory.
A DC-based Semantics for Verilog - Zhu, He (2000) (1 citation) (Correct)
....which will be revisited in Appendix. There have been many experiments in use of Duration Calculus for real time programming. An occam like language was formalised in [18] where a program is identified with two DC formulae, describing terminating and non terminating behaviours respectively. Pace [10] also proposed a denotational semantics for Verilog, but he neglected its shared variable feature. In order to describe that feature, Pandya and Dang proposed to use WDC [11] Xu [14] also gave a denotational semantics based on WDC to a subset of Verilog with shared variable feature. However it ....
Gordon J. Pace. Hardware Design Based on Verilog HDL. Ph.D. Thesis, Oxford University Computing Laboratory, U.K. 1997.
Describing and Verifying FFT circuits using - Sharphdl Gordon Pace (2005) Self-citation (Pace) (Correct)
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Gordon J. Pace, Hardware Design Based on Verilog HDL, Oxford University Computing Laboratory, Programming Research Group. Trinity Term 1998.
Correct Hardware Compilation with Verilog HDL - Pace Self-citation (Pace) (Correct)
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Gordon J. Pace. Hardware Design Based on Verilog HDL. PhD thesis, Computing Laboratory, University of Oxford, 1998.
Correct Hardware Compilation with Verilog HDL - Pace Self-citation (Pace) (Correct)
....for comparing the output of the hardware description without actually having a hardware interpretation from such modules to hardware. Recently, transformations have been implemented in synthesis tools, allowing certain types of behavioural modules to be automatically compiled into hardware. In [Pac98,PH98] we have defined the semantics of Verilog HDL [Ope93,IEE95] a commercial HDL, widely used in industry. As one of the benefits of this formalisation, was the verification of a compilation procedure from a subset of procedural Verilog code to a more hardware oriented subset of the language. The ....
....[HJ94,PL91,May90] except that the output is not a circuit, but another program in the same language. 2 The Semantics of Verilog 2. 1 Modules The semantics of Verilog are given in terms of Relational Duration Calculus [PH98] A more complete presentation of these semantics can also be found in [Pac98]. We assume the reader to be familiar with Duration Calculus [ZHRR91] We assume that each module P has a number of output wires out(P ) to which no other module may write. Also, the assignments to the outputs of a module must take some time. All modules are allowed to read the output variables of ....
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Gordon J. Pace. Hardware Design Based on Verilog HDL. PhD thesis, Computing Laboratory, University of Oxford, 1998.
From Operational Semantics to Denotational Semantics for Verilog - Zhu, Bowen, He (2001) (Correct)
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G. Pace. Hardware Design Based on Verilog HDL. PhD Thesis, Oxford University Computing Laboratory, UK, 1998.
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