Golze, U., VLSI Chip Design with the Hardware Description Language VERILOG. SpringerVerlag, Berlin, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the phase domain and a phase based definition of the clock to output delay; and (c) dependence of the phase based delay on the choice of the phase threshold in the range from to 2. current large scale and very large scale semiconductor digital circuits is based on one of these HDL formats [71] [73]. HDL s are employed to describe the behavior and structure of the circuit at all design levels for the purpose of functional simulation and automated logic synthesis [74] 75] b) c) d) Fig. 9. TAN: Calculating the setup time for a DRO cell using TAN: a) definition of input sequences for ....

U. Golze, VLSI Chip Design with the Hardware Description Language VERILOG. New York: Springer-Verlag, 1996.

....behavioral view must be created for each basic gate in the library. The behavioral view describes the logic function and the timing characteristic of the gate. An acceptable way of creating a behavioral view, adapted from semiconductor circuit design, is the use of an HDL, such as Verilog HDL [5] [18] and VHDL [19] 6] The Rochester design environment supports the use of both of these languages for behavioral modeling and simulation of RSFQ circuits [3] 11] The initial version of a behavioral view is created directly from the cell specification (e.g. a Mealy diagram) and does not ....

U. Golze, VLSI Chip Design with the Hardware Description Language VERILOG. New York: Springer Verlag, 1996.

....try to support the development process and coaching of students. Also, these CBTs are considered implementation examples. AN EXPERIMENT FOR EVALUATION OF CBTS For an even better evaluation, we performed an experiment on a class of 60 students and a special chapter in chip design, logic synthesis [2,3]. The students were divided into three classes: class B was taught the conventional way (classroom plus text book) class A in addition received a logic synthesis CBT, while class C had to get al..ong only with the CBT. Table I shows the distribution of the teaching materials. TABLE I DISTRIBUTION ....

Golze, U., "VLSI Chip Design with the Hardware Description Language VERILOG", Book, 1996, Springer.

....its interactions with the environment, where both input and output are seen an atomic event, and can be detected by an observer. VERILOG HDL is an event based language with shared variable concurrency. In general an event cannot model the state of shared variables, but represents their changes [4]. A VERILOG process interacts with its environment through the events incurred by the changes of the value of shared variables. Usually, the state change detected by the external environment isn t generated by a single assignment statement, but a sequences of imperative statements such as ....

U.Golze. VLSI Chip Design with Hardware Description Language VERILOG. Springer-Verlag, (1996).

....Hardware Description Languages (HDLs) are an increasingly popular way to develop hardware in industry as tool support improves and standards become established. Two of the major HDLs in use are VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language) 52] and VERILOG [17]. Both VHDL and VERILOG have IEEE standards associated with them [35, 36] For extensive on line information relating to VERILOG, see [1] The formal semantics of VHDL has been studied quite extensively [15] but that of VERILOG less so, even though VHDL is probably a more complex language than ....

....time. Of course this rapid prototype system is only suitable for very small VERILOG programs, but it could be a useful aid in the understanding of the semantics of VERILOG programs which is otherwise only generally available in large informal documents such as the IEEE Standard [36] and textbooks [17] or in large software simulators that are necessarily deterministic for efficiency reasons. Epilogue 23 6 Epilogue The Prolog simulator operational semantics for a subset of the VERILOG Hardware Description Language (HDL) presented in this report is pleasingly close to the original operation ....

Golze, U., VLSI Chip Design with the Hardware Description Language VERILOG. SpringerVerlag, Berlin, 1996.

....on the validity of the operational semantics. 1. Introduction The use of formal methods is as successful, if not more successful, in the realm of hardware design as it is in software [20, 21] This paper investigates the formalization of a widely used Hardware Description Language (HDL) Verilog [11]. The use of the Prolog logic programming language [8] to encode this as an operational semantics [30, 33] allows the possibility of direct execution of this formal description. An important feature of a specification is that it is not necessarily executable [4, 14] although some contend that it ....

....Hardware Description Languages (HDLs) are an increasingly popular way to develop hardware in industry as tool support improves and standards become established. Two of the major HDLs in use are VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language) 38] and Verilog [11]. Both VHDL and Verilog have IEEE standards associated with them [23, 24] For extensive online information relating to Verilog, see [1] The formal semantics of VHDL has been studied quite extensively [9] but that of Verilog less so, even though VHDL is probably a more complex language than ....

[Article contains additional citation context not shown here]

Golze, U., VLSI Chip Design with the Hardware Description Language VERILOG. Springer-Verlag, Berlin, 1996.

....to model the structure and behaviour of digital systems ranging from simple hardware building blocks to complete systems. In this section we will introduce Verilog briefly, discussing some semantical problems through examples. This section is based mainly on [7] see also [12] 8] 10] 11] and [6] as well as http: www.cl.cam.ac.uk:80 users mjcg Verilog for some references about Verilog) A specification in Verilog consists of a main module, that specifies a closed system containing both test data and hardware models, consisting of zero or more modules (or blocks) The specification can ....

Ulrich Golze. VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design. Springer Verlag, 1996.

....(HDL) widely used to model the structure and behaviour of digital systems ranging from simple hardware building blocks to complete systems. In this section we will introduce Verilog briefly, discussing some semantical problems through examples. This section is based mainly on [2] see also [7] [3], 5] 6] and [1] as well as http: www.cl.cam.ac.uk:80 users mjcg Verilog for some references about Verilog) A specification in Verilog consists of a main module, which specifies a closed system containing both test data and hardware models, consisting of zero or more modules (or blocks) The ....

....are equivalent (as for example the behavioural and structural version of the DTYPE in Example 2.1. 2) For other semantical challenges of Verilog refer to [2] There are not so many published papers attempting to give formal semantics to Verilog (as far as we know) and some of them are [ [3] and [7] 2.3 Example The following example shows the order between the blocking and non blocking assignments with and without delays. module control; reg [7:0] x, y, z; initial display ( time x y Statement ) always (z) begin x = x 3; write ( 5.0f 5.0f 5.0f , time, x, y) display ( ....

[Article contains additional citation context not shown here]

Ulrich Golze. VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design. Springer Verlag, 1996.

....the exact order of interleaving of parallel execution of processes may not be known. In the simulation of hardware, this is important since hardware systems are naturally parallel, consisting a large number of components, all constantly executing. To model the non determinacy of the simulators [2, 3, 1], we enrich Verilog with the guarded choice Report No. 183, January 2000 UNU IIST, P.O. Box 3058, Macau The Semantical Model of Verilog 2 where its timing control guards represent all the currently enabled actions. Shown in the expansion laws of parallel programs, the guarded choice actually act ....

U. Golze. VLSI Chip Design with the Hardware Description Language VERILOG. Springer, (1996).

No context found.

Golze, U., VLSI Chip Design with the Hardware Description Language VERILOG. SpringerVerlag, Berlin, 1996.

No context found.

Ulrich Golze. `VLSI Chip Design with the Hardware Description Language VERILOG'. SpringerVerlag Berlin Heidelberg, 1996.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC