L. Codrescu, D. S. Wills, and J. D. Meindl. Architecture of the Atlas chipmultiprocessor: Dynamically parallelizing irregular applications. IEEE Transactions on Computers, 50(1):67--82, 2001.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....To further boost the performance, we need to find and exploit different types of parallelism in addition to instruction level parallelism. Speculative thread level parallelism is one such promising approach where sequential programs are dynamically split into threads that execute simultaneously [1,4,9,10,19,20]. These threads are speculatively issued before the dependencies with previous threads are resolved. The advantage of speculative threads is that they provide a coarser granularity for applying parallel execution. One of the most popular points for spawning speculative threads is at methods. In ....

....The Shade analyzer then feeds a summarized account of the program s execution to the SMLP simulator. 3.2. SMLP Execution Model In our model, speculative method level parallelism is supported by a chip multiprocessor (CMP) microarchitecture. Many different CMPs have been proposed in great detail [4,9,10,14,20]. The execution model used in this work encapsulates some of the high level features of these CMPs and is based on the following assumptions. The CMP has eight processors. Each processor is singleissue and in order execution. Each instruction takes one cycle to complete. The system has a ....

L. Codrescu and D. S. Wills, "Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications", in Proceedings of the 1999.

.... At one extreme, speculative thread parallelism has been proposed for large scale shared memory multiprocessors[3, 9, 28] More common proposals, such as those based upon chip multiprocessors, are fairly loosely coupled and typically provide inter thread communication through the level 2 cache[5, 10, 29]. Some propose relatively novel architectures, such as the ring of processing elements found in the Multiscalar [25] The most tightly coupled implementations include the DMT machine[1] which adds speculative thread support to a simultaneous multithreaded (SMT) 33] version of a traditional ....

....If there is a hit, and the confidence values for the prediction entry are sufficiently high, the predicted value will be installed in the return value register for procedure threads, or in the destination register for loads. The value predictor used is the Hybrid Local Global predictor described in[5], but augmented with a 2 bit saturating dependence confidence predictor. If thread T1 meets with thread T2 , and a return value prediction had been made for T2 , the standard register validation process (described in Section 4.2) is used to check the values and restart T2 if necessary. In ....

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L. Codrescu, D. S. Wills, and J. D. Meindl. Architecture of the Atlas chip-multiprocessor: Dynamically parallelizing irregular applications. IEEE Transactions on Computers, 50(1):67--82, 2001.

....(values used but not defined within the thread) at thread start time. Some works mentioned earlier has also used value prediction for module return values [2, 6] and memory loads [12] Others who have used value prediction in conjunction with coarse grained speculative architectures include [13, 1, 3]. However, to the best of our knowledge, our study is the first to address the limits on value prediction which pin points whether there is room for improvements. 6. Conclusions The goal of this study has been to understand the impact of the programming style imperative versus objectoriented ....

L. Codrescu and D. S. Wills. Architecture of the atlas chipmultiprocessor: Dynamically parallelizing irregular applications. In Proceedings of the

....threads. If the ARB detects a violation, it will force all of the speculative threads to be aborted. These threads then must be restarted to use the correct values. Another dimension along which multithreaded architectures can be compared is the level of compiler support they require. The ATLAS [36], Multiscalar [34] and Raw [37] architectures, for example, all expect the compiler to perform different degrees of dependence analysis and program optimization when compared to the superthreaded architecture. As suggested in Figure 6, the ATLAS architec 8 ture makes all thread partitioning ....

Lucian Codrescu and D. Scott Wills, "Architecture of the Atlas chip-multiprocessor: Dynamically parallelizing irregular applications, " in International Conference on Computer Design, October, 1999.

....research is increasingly looking at multithreading to increase parallelism, tolerate latency, and reduce design complexity. A stigma of traditional multithreading is poor performance on legacy sequential binaries. A new class of dynamic multithreaded architectures is emerging to meet this need [2][4][10] 14] These designs automatically extract thread level parallelism from binary applications. A defining feature of these architectures is how threads are extracted. Static thread partitioning is a difficult problem, as the compiler must balance the oftenconflicting needs of data flow, control ....

....far, researchers in this area have presented individual algorithms only in the context of different architectures, making comparisons between algorithms difficult. In this paper, current dynamic partitioning algorithms are quantitatively compared in the context of the Atlas chip multiprocessor [4]. This design starts with a conventional shared memory multiprocessor. Support for thread speculation (multiscalar execution) and aggressive inter thread data value prediction are added. The paper then introduces a new dynamic partitioning algorithm, called MEM slicing. The basic algorithm is ....

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L. Codrescu and S. Wills, "Architecture of the Atlas ChipMultiprocessor: Dynamically Parallelizing Irregular Applications", in ICCD-99, Oct. 1999.

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L. Codrescu, D. S. Wills, and J. D. Meindl. Architecture of the Atlas chipmultiprocessor: Dynamically parallelizing irregular applications. IEEE Transactions on Computers, 50(1):67--82, 2001.

No context found.

L. Codrescu and D. S. Wills. Architecture of the atlas chipmultiprocessor: Dynamically parallelizing irregular applications. In Proceedings of the 1999.

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L. Codrescu and D. Wills, "Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications", IEEE Transactions on Computers, vol. 50, no. 1, pp. 67-82, Jan. 2001.

No context found.

Lucian Codrescu, D. Scott Wills, and James D. Meindl. Architecture of the atlas chipmultiprocessor: Dynamically parallelizing irregular applications. IEEE Transactions on Computers, 50(1):67--82, 2001.

No context found.

Lucian Codrescu, D. Scott Wills, and James Meindl. Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. IEEE Transactions on Computers, 50(1):67--82, 2001.

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