T. Sakata, K. Itoh, M. Horiguchi, and M. Aoki, "Subthreshold-Current Reduction Circuits for MultiGigabit DRAM's," IEEE J. Solid-State Circuits 29, No. 7, 761--769 (July 1994). Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Subthreshold Leakage Modeling and Reduction Techniques - Kao, Narendra, Chandrakasan (2002) (5 citations) (Correct)
....where a degenerating resistor is used to generate the biased source voltage. For high performance, the degenerating resistor is bypassed to ground, but during the standby state, the resistor is used to bias the source terminal of the off device. Another variation known as self reverse biasing [9,10] replaces the switched source impedance with another off transistor so that the equilibrium value is set through a series of off devices. This technique was first applied to decoded wordline driver circuits. 3.2 Stack effect A final example of the source biasing principle is illustrated by ....
T. Sakata, K. Itoh, H. Horiguchi, M. Aoki, "Sub-threshold-Current Reduction Circuits for Multi-Gigabit DRAM's," IEEE JSSC, vol. 29, no.7, pp.761-769, July 1994.
Leakage Power Reduction for Reactive Computation - Favalli, Metra (Correct)
.... of gates is implemented by means of low threshold devices which are gated by high threshold devices placed in series toward ground or power supply: such transistors (suitably sized to maintain acceptable performance) are ON during normal operations, while they are turned off during the idle time [9]# ffl non conventional CMOS technologies (whose discussion, however, is beyond the scope of this paper) 10] All these techniques require process modifications with respect to the standard CMOS one, and, in addition, they present some drawbacks: the threshold voltage is not efficiently ....
.... even if more accurate analysis have recently been proposed accounting for series devices [23] Finally, the value of P switch is very important because it represents the overhead of the proposed method with respect to a standard implementation (notice that the techniques proposed in [8] and [9] also present P switch 0) and it has to be compared with the achieved savings in leakage power when the circuit is idle. Consider the case of a transition between the activeandthe idle circuit configurations, P switch is given by the sum of: a) the power dissipated by applying X idle to C, ....
[Article contains additional citation context not shown here]
T. Sakata, M. Horiguchi, and K. Itoh, "Subthreshold-current reduction circuits for multi-gigabit dram's," in Symposium on VLSI Circuits, 1993.
Deep Sub-micron I_DDQ Testing: Issues and Solutions - Sachdev (1997) (Correct)
....Burr et al. 14,15] used transistor threshold voltage close to 0V by eliminating the threshold implant mask. They subsequently used reverse bias to increase the threshold voltage to a desired value. In this manner, they realized an optimum power delay product for a given circuit. Sakata et al. [16] proposed sub threshold current reduction circuits for Multi Gbit DRAMs. They proposed the hierarchical power line scheme for wordline decoder circuit and sense amplifier driving circuit. The salient feature of the scheme was to utilise decoded address inputs to connect the selected part of the ....
T. Sakata, M. Horiguchi, and K. Itoh, "SubthresholdCurrent Reduction Circuits for Multi-Gigabit DRAMs", Symposium on VLSI Circuits, Digest of Papers, pp. 45-46, 1993.
Review and future prospects of low-voltage RAM circuits - Nakagome, Horiguchi.. (2003) Self-citation (Itoh Horiguchi) (Correct)
No context found.
T. Sakata, K. Itoh, M. Horiguchi, and M. Aoki, "Subthreshold-Current Reduction Circuits for MultiGigabit DRAM's," IEEE J. Solid-State Circuits 29, No. 7, 761--769 (July 1994).
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