W. W. Hwu and Y. N. Patt. Checkpoint repair for out-oforder execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18--26, June 1987. Home/Search Document Not in Database Summary Related Articles Check |
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Efficient Superscalar Performance Through Boosting - Michael Smith Mark (1992) (48 citations) (Correct)
....movement into safe speculative execution, and thus a compiler alone cannot support the general movement of instructions above their control dependent branch. There are numerous hardware techniques that allow dynamic schedulers to safely move any instruction above its control dependent branch [15][21] The basis of all these techniques is the inclusion of extra buffering in the hardware which holds the effects of the speculative operations 1 . The sequential state of the machine is defined as that machine state that is not a result of any speculative operation, and conversely, the ....
W.W. Hwu and Y.N. Patt. Checkpoint Repair for Out-oforder Execution Machines. In Proc. 14th Int. Symp. on Computer Architecture, pp. 18--26, June 1987.
Register Renaming and Dynamic Speculation: an.. - Moudgill, Pingali.. (1993) (17 citations) (Correct)
....Actually, it is not necessary for all the physical registers to be restored to their value at the time the interrupting instruction was issued; it is enough to restore only those registers that were actually mapped at that point. For instance, if we wish to adopt a checkpoint retry mechanism [4] then, at the checkpoint, we would need to save the current map, and the values of the physical registers mapped by the current map. On an interrupt, the checkpointed values would be used to reset the map and the relevant physical registers. The history buffer mechanism is a particularly ....
W.M. Hwu and Y.N. Patt. Checkpoint repair for outof -order execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18--26, June 1987.
Putting the Fill Unit to Work: Dynamic Optimizations for.. - Friendly, Patel, Patt (1998) (33 citations) Self-citation (Patt) (Correct)
....Instructions are dispatched for execution from a 32 entry reservation station associated with each functional unit. A 64KB, 4 way set associative, L1 data cache is used for data supply. It has a load latency of one cycle after the address generation is complete. The model uses checkpoint repair [5] to recover from branch mispredictions and exceptions. The execution engine is capable of creating up to three checkpoints each cycle, one for each block supplied. The memory scheduler waits for addresses to be generated before scheduling memory operations. No memory operation can bypass a store ....
W. W. Hwu and Y. N. Patt. Checkpoint repair for out-oforder execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18--26, 1987.
Improving Trace Cache Effectiveness with Branch Promotion.. - Patel, Evers, Patt (1998) (17 citations) Self-citation (Patt) (Correct)
....engine is composed of 16 functional units, each unit capable of all operations. Instructions are dispatched for execution from a 64 entry reservation station (or node table) associated with each functional unit. A 64KB L1 data cache is used for data supply. The model uses checkpoint repair [6] to recover from branch mispredictions and exceptions. The execution engine is capable of creating up to three checkpoints each cycle, one for each fetch block supplied. The memory scheduler waits for addresses to be generated before scheduling memory operations. No memory operation can bypass a ....
W. W. Hwu and Y. N. Patt. Checkpoint repair for out-oforder execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18--26, 1987.
A Comprehensive Instruction Fetch Mechanism for a Processor.. - Yeh, Patt (1992) (26 citations) Self-citation (Patt) (Correct)
No context found.
W.W. Hwu and Y.N. Patt, "Checkpoint Repair for Out-oforder Execution Machines," IEEE Transactions on Computers, (December 1987), pp.1496-1514.
Checkpoint Processing and Recovery: - Towards Scalable Large (Correct)
No context found.
W. W. Hwu and Y. N. Patt. Checkpoint repair for out-oforder execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18--26, June 1987.
Checkpoint Processing and Recovery: - Towards Scalable Large (Correct)
No context found.
W. W. Hwu and Y. N. Patt. Checkpoint repair for out-oforder execution machines. In Proceedings of the 14th Annual International Symposium on Computer Architecture, pages 18--26, June 1987.
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