R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. GRAPE: A CASE Tool for Digital Signal Parallel Processing. IEEE ASSP Magazine, vol.7, (no.2):32-43, April, 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....consumed by each actor is fixed. Although the model is too restricted for many general purpose applications, iterative SDF has proven to be a useful framework for representing a significant class of DSP algorithms, and it has been used as a foundation for numerous DSP design environments [10] [26], 40] 42] A wide variety of techniques have been developed to schedule SDF specifications for efficient multiprocessor implementation (e.g. 1] 2] 11] 17] 18] 30] 36] 40] 44] and [47] The techniques developed in this paper can be used as a post processing step to improve the ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A case tool for digital signal parallel processing," IEEE ASSP Mag., vol. 7, April 1990.

....techniques to compile graphical DSP programs based on the synchronous dataflow (SDF) model into software implementations that require a minimum amount of memory for code and data. Numerous DSP design environments, including a number of cornmercial tools, support SDF or closely related models [9, 12, 13, 14]. Here, we focus on programs that are represented as acyclic SDF graphs. In SDF, a program is represented by a directed graph in which each vertex (actor) represents a computation, an edge specifies a FIFO buffer, and each actor produces (consumes) a fixed number of data values (tokens) onto ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing," IEEE ASSP Magazine, April, 1990.

....dataflow 1. Introduction As system complexity increases and fast design turn around time becomes important, automatic code synthesis from dataflow program graphs is a promising high level design methodology for rapid prototyping of complicated multimedia embedded systems. COSSAP[1] GRAPE[2], and Ptolemy[3] are well known design environments, especially for digital signal processing applications, with automatic code synthesis facility from graphical dataflow programs. In a hierarchical dataflow program graph, a node, or a block, represents a function that transforms input data ....

....binding strategy, and the size of local buffers in the generated code with static binding strategy. Figure 7(e) and (f) show the code segments that highlight the difference. In this example, using dynamic binding strategy is more advantageous. s(c,2) 1 1 (a) b) c) main( struct G a[2]= g 1,g , b[2] g,g 1 , c[2] g,g 1 ; int in A=0, out A=0, in B=0, out B=0, in C=0, out C=1; for(int i=0;i max iteration;i ) A s codes. Use c[in A] and a[out A] in A = in A 1) 2; out A = out A 1) 2; B s codes. Use a[in B] and b[out B] in B = in B 1) 2; out B = ....

[Article contains additional citation context not shown here]

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing", IEEE ASSP Magazine, vol. 7, (no.2):32-43, April, 1990

....a main component in a memory and cost critical hardware software design, e.g. a singlechip solution. The methodology begins with a given synchronous dataflow graph [14] as used in many rapid prototyping environments as input for code generators for programmable digital signal processors (PDSPs) [5, 13, 17]. Example 2.1 A practical example is a sample rate conversion system. In Fig. 3, a digital audio tape (DAT) operating at a sample rate of 48 kHz is interfaced to a compact disk (CD) player operating at a sampling rate of 44.1 kHz, e.g. for recording purposes, see [23] for details on multistage ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren. Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2):32--43, Apr. 1990.

....connections between them. Each node consumes and produces a predetermined fixed number of delays (i.e. data tokens) on each invocation. Additionally, each edge may contain some initial number of delays. This model has proven popular with designers of signal processing programming environments [10,12,19,24] with its use leading to numerous important results regarding the scheduling [8] hierarchization [22] vectorization [21] and multiprocessor allocation [9, 14] of DSP programs. A great deal of research has been done attempting to optimize various aspects of an application s execution by applying ....

R. Lauwereins, M. Engels, J.A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. GRAPE: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7:32--43, 1990.

....connections between them. Each node consumes and produces a predetermined fixed number of delays (i.e. data tokens) on each invocation. Additionally, each edge may contain some initial number of delays. This model has proven popular with designers of signal processing programming environments [9, 11, 18, 23] with its use leading to numerous important results regarding the scheduling [7] hierarchization [21] vectorization [20] and multiprocessor allocation [8, 13] of DSP programs. A great deal of research has been done attempting to optimize various aspects of an application s execution by applying ....

R. Lauwereins, M. Engels, J.A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. GRAPE: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7:32--43, 1990.

....with its simulator [13] Silage is based on data flow semantics. In the future, extensions of the specification model are envisioned to include control flow semantics, which are needed to characterise the system control and protocol layer. A similar mix of specification models is intended by Grape [11] and Ptolemy [9] ffl Memory management. In order to cope with restrictions on the available memory space and bandwidth, transformations of the control flow specified in the algorithm may be required. Memory management is a global optimisation, in which both the high speed and low speed functions ....

R. Lauwereins, M. Engels, J. Peperstraete, E. Steegmans, J. Van Ginderdeuren, "Grape : a CASE tool for digital signal parallel processing", IEEE ASSP Magazine, April 1990.

.... a dynamic programming technique for reducing memory requirements when synthesizing software from graphical DSP programs that are based on the synchronous dataflow (SDF) model [10] Numerous DSP design environments, including a number of commercial tools, support SDF or closely related models [9, 14, 13, 15, 16]. In SDF 1 , a program is represented by a directed graph in which each vertex (actor) represents a computation, an edge specifies a FIFO communication channel, and each actor produces (consumes) a fixed number of data values (tokens) onto (from) each output (input) edge per invocation. Fig. 1 ....

....in Rate Optimal Schedules, Proceedings of the International Conference on Application Specific Array Processors, August, 1994. 8] W. H. Ho, E. A. Lee, and D. G. Messerschmitt, High Level Dataflow Programming for Digital Signal Processing, VLSI Signal Processing III, IEEE Press, 1988. [9] R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, GRAPE: A CASE Tool for Digital Signal Parallel Processing, IEEE ASSP Magazine, April, 1990. 10] E. A. Lee and D. G. Messerschmitt, Static Scheduling of Synchronous Dataflow Programs 17 for Digital Signal ....

[Article contains additional citation context not shown here]

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing," IEEE ASSP Magazine, April, 1990.

....Lee is with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, CA 94720, USA, eal eecs.berkeley.edu, fax: 510)642 2739. In Proceedings of the International Parallel Processing Symposium, April 1996. Warp compiler [20] DESCARTES [21] GRAPE [11], and the Graph Compiler [23] An important property of SDF graphs is that it is possible to determine efficient schedules for such graphs at compile time. A number of techniques have been proposed for statically scheduling SDF programs for efficient multiprocessor implementation. Parhi and ....

R. Lauwereins, M. Engels, J.A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing," IEEE ASSP Magazine, Vol. 7, No. 2, April, 1990.

....Sciences, University of California at Berkeley. In Journal of VLSI Signal Processing Systems, Vol 21, No. 2, pages 151 166, June 1999. 1999 Kluwer Academic Publishers. 2 1. Introduction Numerous software design environments for digital signal processing applications, such as those described in [6, 14, 16, 23, 24, 27], support code generation for programmable digital signal processors used in embedded systems. Traditionally, programmable digital signal processors have been programmed manually, in assembly language, and this is a tedious, error prone process at best. Hence, generating code automatically is a ....

....edge, are 50, 40, 60, and 50 respectively. Note that this model of buffering maintaining a separate memory buffer for each data flow edge is convenient and natural for code generation, and it is the model used, for example, in the SDF based code generation environments described in [6] [14], 24] More technical advantages of this buffering model are elaborated on in [22] 4. Relative prioritization of code and data minimization objectives There are two natural angles for approaching the problem of joint minimization of code size and buffer memory requirements. The first approach ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing," IEEE ASSP Magazine, Vol. 7, (No.2):32-43, April, 1990.

.... a dynamic programming technique for reducing memory requirements when synthesizing software from graphical DSP programs that are based on the synchronous dataflow (SDF) model [10] Numerous DSP design environments, including a number of commercial tools, support SDF or closely related models [9, 13, 14, 15]. In SDF 2 , a program is represented by a directed graph in which each vertex (actor) represents a computation, an edge specifies a FIFO communication channel, and each actor produces (consumes) a fixed number of data values (tokens) onto (from) each output (input) edge per invocation. 1. A ....

R. Lauwereins et. al, "GRAPE: A CASE Tool for Digital Signal Parallel Processing, " IEEE ASSP Magazine, April 1990.

....time to optimize the memory requirements. On the other hand, as system complexity increases and fast design turn around time becomes important, it attracts more attention to use high level software design methodology: automatic code generation from block diagram specification. COSSAP[1] GRAPE[2], and Ptolemy[3] are well known design environments, especially for digital signal processing applications, with automatic code synthesis facility from graphical dataflow programs. This paper is concerned with memory optimized code synthesis from dataflow programs in case applications deal with ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, " GRAPE: A CASE Tool for Digital Signal Parallel Processing", IEEE ASSP Magazine, vol. 7, (no.2):3243, April, 1990

....each node contains a kernel (code fragment) of a host language tailored to an implementation engine while the dataflow graph itself is a coordination language among function modules. Numerous DSP design environments including a number of commercial tools support SDF or closely related models ( 1][3][4] for both simulation and code generation. Software synthesis from an SDF graph includes determining a feasible schedule and a coding style, both of which affect the memory requirements of the generated software for code and data. One of main scheduling objectives for software synthesis is to ....

....b(n p) will be the same as b(n) at every time period p. Then, the total number of tokens on the graph is bounded. The vector q indicates how many times each node is executed in an iteration of the schedule. We call q the repetition vector. For the SDF graph in figure 1, there is a solution : q = [6 4 3 2] T . A schedule S is a sequence of actor (node) firings. We say that an SDF graph with nonzero repetition vector is consistent, when there is a valid cyclic schedule that returns the graph to its original state after every repetition. A valid schedule activates each node at least once, does not ....

[Article contains additional citation context not shown here]

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, GRAPE: A CASE Tool for Digital Signal Parallel Processing", IEEE ASSP Magazine, vol.7, (no.2):32-43, April, 1990

....and scheduling can be determined at compile time. As a matter of fact, the SDF model is used in industrial DSP design tools, e.g. SPW by Cadence, COSSAP (now) by Synopsys, and Advanced Design System from Hewlett Packard, as well as in research oriented environments, e.g. Ptolemy [8] GRAPE [19], and COSSAP [25] Those systems include code generation tools with code (usually optimized assembly code) stored for each actor in a target speci c library. Typically, code is generated from a given schedule by instantiating actor code in the nal program. Subroutine calls may have unacceptable ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2):32-43, April 1990.

....rule: The number of data values (tokens, samples) produced and consumed by each actor is fixed and known at compile time. The SDF model is used in industrial DSP design tools, e.g. SPW by Cadence, COSSAP (now) by Synopsys, as well as in research oriented environments, e.g. Ptolemy [2] GRAPE [3], and COSSAP [4] Those systems include code generation tools with code (usually optimized assembly code) stored for each actor in a target specific library. Typically, code is generated from a given schedule by instantiating actor code in the final program by code inlining. Subroutine calls may ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren, "Grape: A CASE tool for digital signal parallel processing," IEEE ASSP Magazine, vol. 7, no. 2, pp. 32--43, Apr. 1990.

....and that many important aspects such as deadlock detection and scheduling can be determined at compile time. As a matter of fact, there exist rapid prototyping environments that use SDF graphs or related models as input for code generators for programmable digital signal processors (PDSPs) [5, 11, 13]. As reported by DSP analysts (e.g. the DSPStone benchmarking group [18] today s DSP compilers still produce several 100 s of overhead with respect to assembly code written and optimized by hand. Hence, the hardware capabilities such as zero loop overhead, execution of multiple instructions ....

Lauwereins, R., M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren: 1990, `GRAPE: A CASE Tool for Digital Signal Parallel Processing'. IEEE ASSP Magazine 7(2), 32--43.

....of tokens, and these numbers are known at compile time. In addition, each edge has a fixed number of initial tokens, called delays. SDF is used in numerous commercial and researchoriented design tools for DSP, such as COSSAP [12] from the Aachen University of Technology (now from Synopsys) GRAPE [7] from K. U. Leuven, Ptolemy [5] from U. C. Berkeley, DSP Canvas from Angeles Design Systems, SPW from Cadence, and ADS from Hewlett Packard. 2 Notation and background Fig. 1(a) shows a simple SDF graph. Each edge is annotated with the number of tokens produced (consumed) by its source (sink) ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing," IEEE ASSP Magazine, vol. 7, 1990.

....have a simple firing rule: The number of data values (tokens, samples) produced and consumed by each actor is fixed and known at compile time. The SDF model is used in many industrial DSP design tools, e.g. SPW by Cadence, COSSAP by Synopsys, as well as in research oriented environments, e.g. [4, 12, 15]. In general, a code generation method that generates inline code from a given actor schedule (sequence of actor firings) is assumed. With this model, so called single appearance schedules, where each actor appears only once in a schedule, are evidently program memory optimal. Results on the ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2):32--43, April 1990.

....such as deadlock detection and scheduling can be determined at compile time. As a matter of fact, there exist rapid prototyping environments that use SDF graphs or related models as input for code generators for programmable digital signal processors (PDSPs) Buck, Ha, Lee, and Messerschmitt 1991; Lauwereins, Engels, Peperstraete, Steegmans, and Ginderdeuren 1990; Ritz, Pankert, and Meyr 1992) As reported by DSP analysts (e.g. the DSPStone benchmarking group (Zivojnovic, Martinez, Schlager, and Meyr 1994) today s DSP compilers still produce several 100 s of overhead with respect to assembly code written and optimized by hand. Hence, the hardware ....

Lauwereins, R., M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren (1990, April). Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine 7 (2), 32--43.

....to solve this multi objective optimization problem. The methodology begins with a given synchronous dataflow graph [Lee and Messerschmitt, 1987] as used in many rapid prototyping environments as input for code generators for programmable digital signal processors (PDSPs) Buck et al. 1991, Lauwereins et al. 1990, Ritz et al. 1992] Example 1 A practical example is a sample rate conversion system. In Fig. 1, a digital audio tape (DAT) operating at a sample rate of 48 kHz is interfaced to a compact disk (CD) player operating at a sampling rate of 44.1 kHz, e.g. for recording purposes, see ....

Lauwereins, R., Engels, M., Peperstraete, J. A., Steegmans, E., and Ginderdeuren, J. V. (1990). Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2):32--43.

....trade offs in the 3 dimensional run time program memory data memory space of processor schedules. The methodology begins with a given synchronous dataflow graph [5] as used in many rapid prototyping environments as input for code generators for programmable digital signal processors (PDSPs) [3, 4, 6]. Example 1 A practical example is a sample rate conversion system. In Fig. 1, a digital audio tape (DAT) operating at a sample rate of 48 kHz is interfaced to a compact disk (CD) player operating at a sampling rate of 44.1 kHz, e.g. for recording purposes, see [9] for details on multistage ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2):32--43, April 1990.

....such as MPEG audio decoder and 3D graphics pipeline to present the novelty and usefulness of our approach. 1 Introduction Dataflow graph (DFG) has been a successful representation for DSP algorithms since dataflow semantics is well matched with algorithmic function flow in DSP applications [1][2]. In a dataflow graph of interest in this paper, a node represents a function block and an arc between nodes represents the flow dependency between function blocks. When a node is executed, it consumes a fixed number of data samples from each input arc, and produces a fixed number of samples to ....

....order between the nodes, we can determine the execution order and exploit parallelism in various ways to meet the design objectives. Recently, several design tools use coarse grain dataflow graph as an input specification language for not only algorithm simulation but also automatic code synthesis [2][3] For the latter purpose, the most important scheduling objective is to reduce the memory requirement since the memory is an expensive resource in many embedded DSP systems [4] Thus, active research activities are focused on the code synthesis with minimal memory requirement from the given ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing", IEEE ASSP Magazine, vol.7, (no.2):32-43, April, 1990

....tools that generate code from an algorithm specification and compiler level optimizations. We have not located any comprehensive high level tools intended for low power code development, but several technologies appear to be available to build such tools, especially for DSP applications. Graphical [14] and textual languages [12] have been available for some time that enable one to specify a DSP algorithm in a way that doesn t obscure the natural parallelism and data flow. HYPER LP [4] is a DSP datapath synthesis system that incorporates several algorithm level transformations to uncover ....

Lauwereins, R., Engels, M., Peperstraete, J., and Steegmans, E. (1990). GRAPE: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2),32--43.

....any side effect. With a reallife example such as MP3 decoder, we present the novelty and usefulness of our approach. INTRODUCTION Dataflow graph has been a successful representation for DSP algorithms since dataflow semantics is well matched with algorithmic function flow in DSP applications [1][2]. In a dataflow graph, a node represents a function block such as an FIR filter or a Gain, and an arc between nodes represents the flow dependency as shown in figure 1. A function block may contain states inside, called local states or parameters, for internal use. In general, these states cannot ....

....DSP applications can be naturally expressed. The SDF model allows compile time optimization for efficient implementation because of its static property [1] 1 1 1 1 1 3 Source Sink Gain FIR gain =10 taps = Figure 1. An example SDF graph Recently, several design tools such as GRAPE [2], COSSAP [3] and Ptolemy [10] have used coarse grain dataflow graph as an input specification language for not only algorithm simulation but also automatic code synthesis. Even though SDF has nice features to specify DSP algorithms, it has severe difficulties in representing emerging multimedia ....

R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren, "GRAPE: A CASE Tool for Digital Signal Parallel Processing", IEEE ASSP Magazine, vol.7, (no.2): 32-43, April, 1990.

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R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. GRAPE: A CASE Tool for Digital Signal Parallel Processing. IEEE ASSP Magazine, vol.7, (no.2):32-43, April, 1990.

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