T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs," IEEE Trans. Electron Devices, vol. 40, pp. 118--124, Jan. 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....by Shoji in Ref. 3] using a simple linear RC circuit. Delay uncertainty and noise expressions of coupled resistive interconnect have been presented by Kahng using # and lumped circuit models in Refs. 30,31] The e ects of the coupling capacitance have also been addressed by Sakurai in Ref. [32] based on a coupled RC transmission line model. Estimates of the peak coupling noise voltage based on a coupled RC transmission line model have been presented by the authors in Ref. 33] A two line coupled system is presented in the literature [3,23,30,32,33] to analyze this coupling e ect. A ....

....have also been addressed by Sakurai in Ref. 32] based on a coupled RC transmission line model. Estimates of the peak coupling noise voltage based on a coupled RC transmission line model have been presented by the authors in Ref. 33] A two line coupled system is presented in the literature [3,23,30,32,33] to analyze this coupling e ect. A three line coupled system is presented in Ref. 34] using an RC transmission line model. The CMOS logic gates are approximated by the e ective output resistance; the nonlinear behavior of the MOS transistors is therefore neglected in these analyses [3,30,32 34] ....

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T. Sakurai, Closed-form expression for interconnection delay, coupling, and crosstalk in VLSI's, IEEE Trans. Electron Devices ED-40 (1) (1993) 118}124.

....lines identical from minimum width wire geometries. The geometrical parameters for the wires, width (W) thickness (T) spacing (S) resistivity (p) and the inter layer dielectric thickness (H) values are taken from [14] Sakurai s formulas are used to generate the electrical circuit elements [15]; but any similar model could be used. The experiment is done for variations in W, T, S, H and p assuming uniform distributions with tolerances specified in [14] The wires are divided into coupled RC segments at each micron length. The delays are evaluated for 100 samples which are generated by ....

....path is analyzed in the presence of device and wire parameters. Throughout the simulations 0.18 micron MOSFET models are used. The nominal and 3 tolerances for 0. 18 micron device and wire technology parameters are taken from [14] As in Example 2, the electrical parameters are computed via [15]. For simplicity, each variation terms are assumed as independent distributed normal random variables. Similarly, one could use the PCA method to obtain an uncorrelated set out of the measure data. A Monte Carlo analysis with 100 samples is performed via SPICE and TETA using the analytical ....

Sakurai, T. "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs", IEEE Trans. ED, vol 40. Jan 1993

....shape to the nearest available litho width will give virtually no degradation in the wire delay. The staircase shape can be stamped out just as easily as any other mask shape. 2. Capacitance and Inductance Models Consider a wire segment of width . and thickness , Sakurai s formula [16] is a good approximation for calculating the unit length capacitance. The formula can be simplified as 02143516 87:9 . 7( 1) 7 9 A B 3 DC 3 is the unit length area capacitance, 7 = B 3 C 3 95G H H H is the unit length fringing capacitance, and B 3 is the ....

T. Sakurai, Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's, IEEE Transactions on ED, vol.40, No.1, 1993.

....achieved. 1. Introduction As the CMOS technology scaled down into deep sub micron region, the horizontal coupling capacitance between adjacent wires becomes dominant for wire load[1] The increase of inter wire coupling capacitance makes crosstalk interference a serious problem for VLSI circuits[3, 7]. Crosstalk causes logical malfunctions and delay faults. Especially for an on chip bus, crosstalk noise is a serious problem for modern and future VLSI design[8, 4] Since each line of a bus runs in parallel for a long distance, the inter wire coupling capacitance between adjacent wires of the ....

.... (4 2v)Cm . 2) From the equation of 50 bus delay with k repeaters[2] whose on resistance and input capacitance are represented as R t and C t , the total bus delay with center wire s timing shift can be represented as following equation. C 0 (4 2v)C m ] 0.7(kR t R)C t . 3) From [7], v can be approximated as v = # # V 1,3 (#T ) V 1,3 (0) # # =1 K 1 exp (4) where C = C 0 2Cm , 6 7 8 9 10 11 bus delay [ns] k = 2 k = 4 k = 6 Figure 5: The relation between shifting time #T and total bus delay T d calculated from eq. 5) C 0 =500fF, ....

T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's. IEEE Trans. on Electron Devices, 40(1):118--124, January 1993.

....is assumed to occur when the victim and aggressor signals switch at the same time and with same transition times (or, typically, assuming no transition time i.e. a step input) Such assumptions are used throughout the industry and academia to provide an upper bound on capacitive coupling. [11] demonstrates that SF = 2 yields pessimistic results; since this result, designing circuits and interconnects with an SF = 2 assumption has been the de facto industry standard. In [10] the time average of effective capacitance is shown to be 2C c . The authors of [13] suggest that using 2C c as an ....

T. Sakurai, "Closed-form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's", IEEE Trans. on Electron Devices 40 (1993), pp. 118-124.

....since they have lower noise margin. To make sure a final layout to be noise immune, accurate yet efficient noise models are needed to guide interconnect optimizations at various stages. Recently, a number of simple crosstalk noise models were proposed. By solving telegraph equations directly, [3, 4] obtained a set of analytical formulae for peak noise of capacitively coupled bus lines. But their approaches handle only fully coupled bus structures, not partially coupled lines or general RC trees. The work in [5] modeled each aggressor and victim net by an L type RC circuit and obtained ....

T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs," IEEE Trans. on Electron Devices, vol. 40, pp. 118--124, 1993.

....voltage, increases. The effect of the coupling noise is also important in dynamic CMOS circuits, which are more sensitive to noise than static CMOS circuits. In the design of high speed VLSI circuits, it is therefore important to be able to predict coupling noise at the system (or chip) level [8]. This information permits circuit malfunctions or extra power consumption caused by the coupling noise to be avoided [9] The design cycle and cost can therefore be reduced as well as the circuit reliability improved. An analysis of coupling noise can be performed in both the frequency domain ....

T. Sakurai, "Closed-Form Expression for Interconnection Delay, Coupling, and Crosstalk in VLSI's," IEEE Transactions on Electron Devices, Vol. 40, No. 1, pp. 118-124, January 1993.

.... is the current reflection number given by , the notation is defined as the decimal truncation of (i.e. and and are determined to obtain the desired accuracy of solution (in the limit they both go to infinity) 23] Using a near wave front approximation to (15) and a distributed model in [24], the 50 time delay of a single Fig. 9. Comparison of distributed rc and distributed rlc model for a global interconnect with Z =266:5 W, r =37:87 W cm, L = 3:6 cm, R =0. interconnect device with the inclusion of inductance can be approximated by (17) where is a step function. Inductance ....

....dimensions to maximize wire density. An existing distributed interconnect model with a step response excitation voltage predicts that the peak crosstalk (at the load of the quiescent line) between the two parallel wires is length, scaling, and material independent for homogeneous dielectrics [24]. 312 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001 The finite switching time of a interconnect driver, however, must be considered to fully understand crosstalk limits for local and semiglobal interconnects. Using a ramp response ideal voltage source driving an active line parallel to a ....

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T. Sakurai, "Closed-form expression for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118--124, Jan. 1993.

....approximation properties of known methods and to discuss, also briefly, research being developed in this matter. Introduction As widely known, research in adaptive IIR filtering was pursued following two differentiated research lines: stability theory [1, 2] and system identification theory [3]. The first line, closely related to tuning aspects of adaptive control, was aimed at intrinsic stability properties of the filter s parameters being estimated without regarding specific model approximation issues. As a result of intensive work, a rigorous, complete and useful theory was obtained. ....

....comments addressing current research lines in this area. continued on Page 4 4 Prediction Error Methods and Related Algorithms Prediction error methods are a paradigm of system identification theory because statistically efficient estimates can be obtained under wide general conditions [3]. Adequateness of these methods for adaptive filtering, i.e. use of constant step size and limited information about model order, gives place to many algorithms. In order to obtain an approximation H (z) or y(n) B n ( z ) A n ( z ) x(n) with the input output description) of an stable, ....

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T. Sakurai, "Closed-Form Expression for Interconnection Delay, Coupling, and Crosstalk in VLSI's", IEEE Transactions on Electron Devices, vol. ED40, no. 1, pp. 118--124, January 1993.

....[8] used in our approach) Alternatively, we may also use analytical formulae. From the above estimated resistance and capacitance together with driver and receiver characteristics information, we can estimate the crosstalk noise in PPA by any crosstalk modeling, including those in [12] 19] [24] [25] 27] In our implementation, we use a simple closed form conservative formula for two terminal nets described in [25] to calculate the crosstalk noise on each wire segment. 2 According to [25] the peak crosstalk noise V noise for the circuits in Figure 2 can be estimated by the following ....

T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs. IEEE Trans. on Electron Devices, 40:118--124, 1993.

....BACPAC. Other systemlevel models typically use corner to corner lines, which are increasingly rare due to efficient floorplanning tools. At this point, total cycle time is found using average wirelengths (local and global) device and repeater sizes, and a delay expression formulated by Sakurai [13]. We add a term to this expression to account for input rise time dependency based on [14] This term can account for 30 or more of the total stage delay. Latch set up times and propagation delays are also included in the overall clock cycle and these times are based on ASIC libraries. The ....

....maximum local skew corresponding to line length L. amount of skew allowable in the design. The total distance that must be traversed in this instance is L, where L is the side length of a cluster. In order to find the maximum L that meets the T skew requirement, we use Sakurai s delay expression [13] to find the delay between a point just at the output of the buffer and the point in the corner of the cluster (see Figure 3) In this case, we expect the dominant source of delay to be the charging of latch capacitances along the wire resistance. Since these latches will not be lumped at the end ....

[Article contains additional citation context not shown here]

T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Transactions on Electron Devices, vol. 40, pp. 118-124, Jan. 1993.

....[5] used in our approach) Alternatively, we may also use analytical formulae. From the above estimated resistance and capacitance together with driver and receiver characteristics information, we can estimate the crosstalk noise in PPA by any crosstalk modeling, including those in [6] 11] [15] [16] 18] In our implementation, we use a simple closed form formula for two terminal nets described in [16] to calculate the crosstalk noise on each wire segment. 2 According to [16] the peak crosstalk noise Vnoise for the circuits in Figure 2 can be estimated by the following formula: ....

T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs. IEEE Trans. on Electron Devices, 40:118--124, 1993.

....since they have lower noise margin. To make sure a final layout to be noise immune, accurate yet efficient noise models are needed to guide interconnect optimizations at various stages. Recently, a number of simple crosstalk noise models were proposed. By solving telegraph equations directly, [3, 4] obtained a set of analytical formulae for peak noise of capacitively coupled bus lines. But their approaches handle only fully coupled bus structures, not partially coupled lines or general RC trees. The work in [5] modeled each aggressor and victim net by an L type RC circuit and obtained ....

T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs," IEEE Trans. on Electron Devices, vol. 40, pp. 118--124, 1993.

....should be estimated at the system level. The coupling noise voltage on a quiet interconnect line has been analyzed by Shoji using a simple linear circuit in [1] The effects of the coupling capacitance have also been addressed by Sakurai using a resistive capacitive interconnect model in [8], in which the CMOS logic gates are approximated by the effective output resistance and similar interconnect lines are assumed. An estimate of the peak coupling noise voltage based on a coupled transmission line model has been presented by the authors in [9] The nonlinear behavior of the MOS ....

....by the effective output resistance and similar interconnect lines are assumed. An estimate of the peak coupling noise voltage based on a coupled transmission line model has been presented by the authors in [9] The nonlinear behavior of the MOS transistors is neglected in these analyses [1] [8], 9] The maximum effective load capacitance, i.e. the intrinsic load capacitance plus two times the coupling capacitance ( 1352 ) is typically used to estimate the worst case propagation delay of an active logic gate [1] 8] In this paper, a transient analysis of two capacitively coupled ....

[Article contains additional citation context not shown here]

T. Sakurai, "Closed-Form Expression for Interconnection Delay, Coupling, and Crosstalk in VLSI's," IEEE Transactions on Electron Devices, Vol. ED-40, No. 1, pp. 118--124, January 1993.

....since they have lower noise margin. To make sure a final layout to be noise immune, accurate yet efficient noise models are needed to guide interconnect optimizations at various stages. Recently, a number of simple crosstalk noise models were proposed. By solving telegraph equations directly, [10, 7] obtained analytical formulae for peak noise of capacitively Current address: IBM T.J. Watson Research Center, Yorktown Heights, NY, 10598. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made ....

T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs. IEEE Trans. on Electron Devices, 40:118--124, 1993.

....delays for different interconnections (the strips made from different material) differ between each other in accordance to theory owing to the differences of the line capacitances and resistances. 4. COMPARISON WITH THEORETICAL MODELS The simplified model of inverter delay is presented in fig. 2 [1, 2, 3, 4, 5]. V in V out C int C gate R tr V in V out t pd = R tr C gate C int ( Fig. 2. Model of gate delay. The gate delay is determined by the on resistance of the driver R tr and capacitances of the interconnection and the receiving gate C int, C gate . To a first order model parameters ....

....that case. The accuracy of such an approach is better for big values of load capacitance. t pd = R tr C gate C jD C int ( R tr = measured (simulated) value C gate C jD C int ( 4) For long or lossy wires the resistance of interconnection R int must be taken into account [1, 2, 4, 5]. The proper model of the interconnection is RC distributed line model. The good analytical solution for RC distributed line driven by resistance exists [4, 5] However any analytical model is applicable in general when C j and R int are significant. For the measured chip omitting the resistance ....

[Article contains additional citation context not shown here]

T. Sakurai, "Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's," IEEE Trans. on ED, vol. 40, No. 1, pp. 118-123, Jan. 1993.

....sizes. Also, due to decreasing noise margins and larger ground bounce, noise issues become even more important. There is a need for accurate yet fast methods to analyze on chip crosstalk. Previously presented crosstalk models typically ignore wiring resistance [1,2] or apply only to step inputs [3]. Our model is simple, accurate and provides an excellent basis for a crosstalk screening tool. We demonstrate its accuracy in future generation logic gates, concentrating on inverters and NAND gates. The model can be used in conjunction with timing macromodels or other timing models, as driver ....

....noise, V max , can be found by differentiating (2) as this peak always occurs at t T r . 3) Here Y 1 = exp( T r t 1 ) 1 and Y 2 = exp( T r t 2 ) 1. For slow rise times (T r t 2 ) 3) can be seen to approach a limiting value of R v C c V dd T r . Also, the model presented in [3] is a special case of (3) when R a = R v , C a = C v and the gate output is a step. Thus, the model can be seen to have wider applicability than those presented previously. Deep submicron interconnect cannot be effectively modeled by a lumped RC model. However, to derive a simple analytical model, ....

T. Sakurai, "Closed-form expressions for interconnection delay, coupling and crosstalk in VLSI," IEEE Trans. Elec. Dev., v. 40, pp. 118-124, Jan 1993.

....is assumed to occur when the victim and aggressor signals switch at the same time and with same transition times (or, typically, assuming no transition time i.e. a step input) Such assumptions are used throughout the industry and academia to provide an upper bound on capacitive coupling. [11] demonstrates that SF = 2 yields pessimistic results; since this result, designing circuits and interconnects with an SF = 2 assumption has been the de facto industry standard. In [10] the time average of effective capacitance is shown to be 2C c . The authors of [13] suggest that using 2C c as an ....

T. Sakurai, "Closed-form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's", IEEE Trans. on Electron Devices 40 (1993), pp. 118-124.

....than a tier j if the layers of tier i are below (above) the ones of tier j. A tier i is fatter than a tier j if its wire height is larger. 2.2 Delay equation and repeater model The delay model is important since the method is driven by the delay constraint. We use Sakurai s delay equation [7] Td = 0:377RwCw 0:693 (Ro (C j C i ) RoCw RwC i ) 1) with Rw and Cw the wire resistance and capacitance, Ro the (effective) output resistance of the gate that drives the wire and C j and C i the junction and input capacitances of the gate that is driven by the wire. The delay can be ....

T. Sakurai. "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's." IEEE Trans. Electron Devices, 40: pp. 118--124, 1993.

....current return paths. estimation of process variation at all intermediate levels of the Htree. On the other hand, local skew is determined mainly by the size of a cluster (smallest component of an H tree) and localized process variation at the last level of buffering. Based on the delay model of [15], the expression for local clock skew becomes: device wire 2 latches wire 2 wire wire 2 skew LR C 1 . 1 693 . 0 LC R 1 . 1 L C R 1 . 1 377 . 0 T = 4) The factors of 1.1 account for 10 variation in key parameters such as wiring resistance, capacitance, and device ....

T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. on Electron Devices, v. 40, pp. 118-124, Jan. 1993.

....slew rate of aggressor source voltage) times the coupling capacitance. It is implicitly assumed that the aggressor signal slope does not degrade downstream from the aggressor source. Hence, for longer lines this approach can produce either overestimated or underestimated peak noise values. Sakurai [10] solves partial differential equations for coupled RC lines to derive noise and delay expressions. However, driver modeling is not considered and the analysis is limited to step response. Kawaguchi and Sakurai [5] use the diffusion equation to analyze capacitively coupled interconnects, but also ....

T. Sakurai, "Closed form expressions for interconnection delay, coupling and crosstalk in VLSIs", IEEE Transactions on Electron Devices, Jan. 1993, vol. 40(1), pp. 118-124.

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T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs," IEEE Trans. Electron Devices, vol. 40, pp. 118--124, Jan. 1993.

No context found.

T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron. Devices, vol. 40, pp. 118--124, Jan. 1993.

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T. Sakurai. Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's . IEEE Trans. on Electron Devices, 40(1):118--124, January 1993.

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T. Sakurai, "Closed-form expression for interconnection delay, coupling, and cross talk in VLSIs," IEEE Transactions on Electron Devices, Vol. 40, 1993, pp. 118-124.

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