M. D. Hill, J. R. Laurus, A. R. Lebeck et al., WARTS: Wisconsin Architectural Research Tool Set, Computer Science Department University of Wiscocnsin.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....(3) 3.3 Design Flow of our Framework The input is a C program (Fig. 1) of the application 5 .The upper branch comprises a behavior simulator [23] that is attached to our software energy and performance models (Eq. 2 and 3) The branch below contains the trace tool QPT and the Dinero III [19]cache simulator who feeds software, cache and main memory energy models with the numbers of total cache accesses, data cache hits, data cache misses and instruction fetch misses. Output are the numbers for software energy dissipation and performance numbers. The feedback loop contains an ....

M. D. Hill, J. R. Laurus, A. R. Lebeck et al., WARTS: Wisconsin Architectural Research Tool Set, Computer Science Department University of Wiscocnsin.

.... to calculate the energy consumption depending on the instruction executed at a point in time (the same methodology as in [12] is used) Analytical models for main memory energy consumption and caches are fed with the output of a cache profiler that itself is preceded by a trace tool (both: [17]) Finally, the total energy consumption is calculated and it is tested whether the total system energy consumption could be reduced or not. If not then the whole procedure can be repeated and the designer will make use of his her interaction possibilities to provide the partitioning algorithms ....

M. D. Hill, J. R. Laurus, A. R. Lebeck et al., WARTS: Wisconsin Architectural Research Tool Set, Computer Science Department University of Wiscocnsin.

....In this section, we discuss hardware cost, miss ratio, cache access time, and performance both for the VLS cache and for comparable conventional caches. We have made a VLS cache simulator written in C to measure miss ratios. This simulator is given address traces which are captured by QPT [4]. In this section, it is assumed that processor speed is 200 MHz, DRAM start up time is 40 ns, and cache capacity is 16 KB. We compare following models: ffl F32D, F64D, F128D : Conventional direct mapped caches with fixed 32 byte, 64 byte, and 128 byte lines, respectively. ffl F32W4 : A ....

Hill, M. D., Larus, J. R., Lebeck, A. R., Talluri, M., and Wood, D. A., "WARTS: Wisconsin Architectural Research Tool Set," http://www.cs.wisc.edu/~larus/warts.html, University of Wisconsin - Madison.

....The input is an application program. It is fed into a behavioral model of the target processor that simulates the program and delivers a program trace to the software energy model and the software performance model. At the mean time, the input program is also fed into the memory trace profiler QPT [13] which generates the memory access trace to be used by Dinero[13] Dinero provides the number of demand fetches and demand misses (for data and instructions) These numbers are then used: by the software performance model to get the total execution time with cache miss penalty considered (Eq.6) ....

....model of the target processor that simulates the program and delivers a program trace to the software energy model and the software performance model. At the mean time, the input program is also fed into the memory trace profiler QPT [13] which generates the memory access trace to be used by Dinero[13]. Dinero provides the number of demand fetches and demand misses (for data and instructions) These numbers are then used: by the software performance model to get the total execution time with cache miss penalty considered (Eq.6) by the software energy model to adjust the software energy with ....

M. D. Hill, J. R. Laurus, A. R. Lebeck et al., WARTS:Wisconsin Architectural Research Tool Set, Computer Science Department University of Wisconsin.

....system, and a context switch occurs per execution of one million instructions. Mix int1 and mix int2 contain integer programs only, and mix fp consists of three floating point programs. Mix intfp is formed by two integer and one floating point programs. We captured address traces using QPT[4] of each benchmark set for the execution of three billion instructions. Average memory access time (AMT = HitTime MissRate2MissP enalty) is a popular metric to evaluate the cache performance. Miss penalty in merged DRAM logic LSIs can be a constant time regardless of the cache line sizes, ....

Hill, M. D., Larus, J. R., Lebeck, A. R., Talluri, M., and Wood, D. A., "WARTS: Wisconsin Architectural Research Tool Set," http://www.cs.wisc.edu/~larus/warts.html, University of Wisconsin - Madison.

....to compute the number of penalty cycles that must be added to the delay computation in order to take into account the effects of the cache. TRACE GEN is used to optionally generate output traces in a textual file, in order to run a more precise batch cache simulation afterwards (e.g. using DINERO [19], CVT [22] HISTORY LENGTH defines the number of previous paths to consider during inter task conflicts analysis. THRESHOLD defines the minimum value of conflict (between basic blocks during intra task conflicts analysis and between tasks during inter task conflict analysis) to consider. ....

M. ~ D. Hill, J. ~ R. Larus, and A. ~ R. Lebeck. Warts: Wisconsin architectural research tool set. Computer Science Department University of Wisconsin, 1997.

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