Z. Lemnios y K. Gabriel, "Low-Power Electronic", IEEE Design & Test of Computers, pp.8-13. Winter 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and the datapath, synchronisation, and off chip power increments. This effect have been validated experimentally by the construction and measurement of a self timed pipeline multiplier on FPGAs. I. Introduction The relation between logic depth and power consumption is well known [Cha92] [Lem94]. It can be explained by considering that the average dynamic power consumption of a CMOS circuit is: P = c f V all nodes n n DD 2 [1] where V DD is the power supply voltage, c n the capacitance of each node, and f n the actual frequency of each node. Thus, via f n , the dynamic power ....

Z. Lemnios y K. Gabriel, "Low-Power Electronic", IEEE Design & Test of Computers, pp.8-13. Winter 1994.

....manually path equalized version of the same circuit just exhibed 5 to 8 intermediate values. FPGA user has three ways to diminish glitches: pipelining, partitioning improvements and path delay equalization. Pipelining, a popular way to speed up circuits also allows power consumption to be reduced [3] [4] Its usefulness is based on a marginal effect of the intermediate pipeline registers: the obstruction of the propagation of spurious (asynchronous) transitions. Pipelining also affects power consumption by the modification of datapath wiring loads: global lines (which usually broadcast the ....

Z. Lemnios y K. Gabriel, "Low-Power Electronic", IEEE Design & Test of Computers, pp. 8-13, winter 1994.

....has become one of the bottlenecks to the realization of a VLSI chip. Modern microprocessors like PowerPC, Alpha and Pentium are no exceptions to this problem and hence a drive to investigate into power estimation tech2 niques and low power methodologies. Thus, there have been major efforts [63] to reduce the power consumption, at all levels of abstraction in the design flow[40, 37, 38, 71, 90, 69, 91] In order to do so, accurate power estimation techniques are desired. At the lower levels of abstraction, although accurate power estimation is possible, it is very time consuming. Thus, ....

Z.J. Lemnois, K.J. Gabriel, "Low-Power Electronics", IEEE Design & Test of Computers, pp. 8-13, Winter 1994.

....i Architectural Power Estimation Based On Behavior Level Profiling 1 Introduction Due to the increasing demand for portable applications and the rapidly growing complexity, power consumption has become one of the main issues in the realization of VLSI chips. There have been major efforts [2] to reduce the power consumption at all levels of abstraction in the design flow. Accurate power estimation techniques are the key to the success of these efforts. Although accurate power estimation is possible at the lower levels of abstraction, it is very time consuming. Hence, recently focus ....

Z.J. Lemnois, K.J. Gabriel, "Low-Power Electronics", IEEE Design & Test of Computers, pp. 8-13, Winter 1994.

.... in well designed synchronous systems, they can be responsible of up to the 70 of the circuit activity [1] The useless consumption caused by glitches can be decreased in two ways: equalizing all circuit paths [2] 4] or inserting intermediate registers or latches to reduce the logic depth [5], 6] Although the relationship between logic depth and power consumption has been exhaustively analyzed in a wide variety of technologies and topologies [7] 8] the cost of chip fabrication constrained most of these studies to simulation based results. This paper intends to contribute to this ....

Lemnios and K. Gabriel, "Low-Power Electronic", IEEE Design & Test of Computers, pp. 8-13, Winter 1994.

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