B. L. Hutchings and M. J. Wirthlin, "Implementation approaches for reconfigurable logic applications," in Field-Programmable Logic and Applications (FPL'1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... used in networking applications, where they o#er both the performance of custom hardware and the flexibility of reprogrammability [1] 2] Systems implemented with FPGAs can make use of their reprogrammability in one of two ways: Compile Time Reconfiguration (CTR) or Run Time Reconfiguration (RTR) [3]. CTR systems do not change the FPGA s configuration for the lifetime of the application, e.g. SPLASH [4] and PAM [5] RTR systems change the FPGA configuration during the course of operation, either by full reconfiguration [6] 7] or partial reconfiguration [8] 9] 10] The present research ....

B. L. Hutchings and M. J. Wirthlin, "Implementation approaches for reconfigurable logic applications," in Field-Programmable Logic and Applications (FPL'1995.

....can be determined using ordinary satisfiability solvers. 1 Introduction Reconfigurable Computers (RC) contain field programmable processors and interconnect elements whose logic and communication structures can adapted to best suit the computation and communication requirements of an application [2]. Many commercial RCs today use Field Programmable Gate Arrays (FPGA) as the processing elements and programmable interconnection networks based on simple configurable routing elements [3] Figure 1 shows the general architecture of a reconfigurable computer. FPGA FPGA FPGA FPGA Network ....

B. L. HUTCHINGS AND M. J. WIRTHLIN. Implementation Approaches for Reconfigurable Logic Applications. In International Worlshop on Field-Programmable Logic and Applications, FPL, pages 419-428, Springer, 1995.

....reconfiguration approach for multi FPGA systems. Keywords: multi FPGA systems, hierarchical runtime reconfiguration, communication channel synthesis 1 Introduction During the last years run time reconfiguration of hardware has gained interest as implementation approach for embedded systems [1] [2]. Run time reconfigurable systems split a larger problem into temporally exclusive collections, so called configurations, of smaller subproblems that are loaded onto FPGAs dynamically during the application s run time. The design and implementation of these systems pose new research problems. The ....

HUTCHINGS, B. L. and WIRTHLIN, M. J. Implementation Approaches for Reconfigurable Logic Applications. In International Workshop on Field-Programmable Logic and Applications, pages 419--428, 1995.

..... 14 5 1 Introduction Field Programmable Gate Arrays (FPGAs) enable hardware circuits to be reconfigured an unlimited number of times. The implementation of a system that uses reconfigurability can be done in two ways: CompileTime and Run Time Reconfiguration [1]. For Compile Time Reconfiguration (CTR) the FPGA does not change configuration during the application lifetime. Each application has specific functions that are loaded when the FPGA is started. Some examples of CTR systems are SPLASH [2] and PAM [3] For Run Time Reconfiguration (RTR) the FPGA ....

B. L. Hutchings and M. J. Wirthlin, "Implementation approaches for reconfigurable logic applications," in Field-Programmable Logic and Applications (FPL'

....to the computation, increasing runtimes without performing useful work. One method to reduce this reconfiguration overhead is to begin loading the next configuration before it is actually required. Specifically, in systems with multiple contexts [Bolotski94] partial run time reconfigurability [Hutchings95], or tightly coupled processors [DeHon94, Razdan94, Wittig96, Hauck97] it is possible to load a configuration into all or part of the FPGA while other parts of the system continue computing. In this way, the reconfiguration latency is overlapped with useful computations, hiding the reconfiguration ....

....of reconfigurable systems by 41 to 65 , which will have a direct impact on the performance of reconfigurable systems. We believe that such techniques will become even more critical for more advanced reconfigurable systems. When one considers techniques such as partial Run Time Reconfiguration [Hutchings95] or multiple contexts, this greatly increases the amount of computation available to overlap with the reconfiguration, since prefetching can be overlapped with other computations in the reconfigurable logic. We plan to explore the application of prefetching to such advanced systems in our future ....

B. L. Hutchings, M. J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Applications", in W. Moore, W. Luk, Eds., Lecture Notes in Computer Science 975 - Field-Programmable Logic and Applications, London: Springer, pp. 419-428, 1995.

....Framework We strivetodevelop design tools for run time reconfiguration that will become standard in future synthesis systems. From experience, the desirable features for such tools include: 2 ffl the ability to produce a wide range of implementations that are globally or locally reconfigurable [14], covering devices that provide special hardware for rapid reconfiguration# ffl support for simulating, optimising and validating designs at various levels of abstraction# ffl facilities assisting design reuse and performance analysis so that optimal designs can be produced rapidly. This ....

HUTCHINGS, B. and WIRTHLIN, M.J.: `Implementation Approaches for Reconfigurable Logic Applications', Field Programmable Logic and Applications, LNCS 975, Springer, 1995, pp. 419--428.

....computing has gained interest not only as a potentially new paradigm for general purpose computing but also for embedded systems. Reconfigurable systems are often classified according to their reconfiguration model into compile time reconfiguration (CTR) and run time reconfiguration (RTR) [7]. In CTR, hardware compilation and reconfiguration, i.e. downloading the design onto a reconfigurable device, are done at compile time. In embedded systems, this reconfiguration model is mainly used for rapid prototyping. However, reconfigurable hardware can be a viable alternative to ASICs for ....

....channels. In this case, some form of multiplexing logical channels over physical wires must be used. Communicating tasks mapped onto FPGAs that are not directly connected require the insertion of routing nodes. Second, a problem unique to RTR systems is interconfiguration communication [7]. If two communicating tasks are executed sequentially, a means of transferring the data from the sender task to the receiver task must be provided. Given a partially reconfigurable FPGA device, such as the Xilinx XC62xx, part of the FPGA area can be reserved to implement a communication bu#er. In ....

Brad L. Hutchings and Michael J. Wirthlin. Implementation Approaches for Reconfigurable Logic Applications. In International Workshop on Field-Programmable Logic and Applications, pages 419--428, 1995.

....reconfiguration approach for multi FPGA systems. Keywords: multi FPGA systems, hierarchical runtime reconfiguration, communication channel synthesis 1 Introduction During the last years run time reconfiguration of hardware has gained interest as implementation approach for embedded systems [1] [2]. Run time reconfigurable systems split a larger problem into temporally exclusive collections, so called configurations, of smaller subproblems that are loaded onto FPGAs dynamically during the application s run time. The design and implementation of these systems pose new research problems. The ....

HUTCHINGS, B. L. and WIRTHLIN, M. J. Implementation Approaches for Reconfigurable Logic Applications. In International Workshop on Field-Programmable Logic and Applications, pages 419--428, 1995.

....using standard protocols such as the CAN bus or dedicated links based on built in facilities such as DMA channels. Run time reconfiguration (RTR) of FPGAs is gaining interest for embedded system design as it enlarges the design space by allowing to execute timeexclusive system parts sequentially [9, 14] on a moderately sized FPGA device. The challenge is to design e#cient RTR systems in terms of reconfiguration time (system performance) and area overhead (implementation cost) A further important issue is the synthesis of communication channels between heterogeneous components [11, 12] on one ....

.... reconfiguration time (system performance) and area overhead (implementation cost) A further important issue is the synthesis of communication channels between heterogeneous components [11, 12] on one hand and between time exclusive system parts on the other hand (interconfiguration communication [9, 7, 6]) Most current approaches for reconfigurable system design focus on aspects such as optimal partitioning [3] scheduling [4, 13] or communication synthesis [12] We learned through our previous work [7] that dynamic reconfiguration of FPGAs sometimes leads to remarkable overheads in terms of ....

B. Hutchings and M. Wirthlin. Implementation Approaches for Reconfigurable Logic Applications. In International Workshop on Field-Programmable Logic and Applications, pages 419--428, 1995.

.... programming) technology the FPGA (field programmable gate arrays) components gained competitive advantages in the implementation of reconfigurable computing systems, instead of their typical role in the temporary and precarious replacement of the expensive MPGAs (mask programmable gate arrays) [Hutchings et al. 1995]. The list of reconfigurable systems based on ISP FPGAs (FCCMs FPGA based custom computing machines) is increasingly growing [Guccione list] although some architectural design trade offs are still under study [Esteves et al. 1997] namely, the granularity of the reconfigurable hardware ....

Hutchings, Brad L. and Michael J. Wirthlin, Implementation Approaches for Reconfigurable Logic Applications, Field- -Programmable Logic Applications, LNCS 975, Springer, 1995.

....possible. Initial work has already been done on several techniques for configuration management: Multi context FPGAs (a form of on chip cache for configurations) to maintain data in the FPGA [Bolotski94, Trimberger97] Compression [Dehon96, Hauck98d, Hauck98e] and partial Run Time Reconfiguration [Lysaght94a, Churcher95, Hutchings95, Wirthlin95, Rupp98] techniques to reduce the amount of data that must be transferred; Prefetching algorithms to preload the next needed configuration and thus overlap computation with reconfiguration [Hauck98a] Parallel configuration buses to increase reconfiguration bandwidth [Churcher95] While these techniques ....

B. L. Hutchings, M. J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Applications", in W. Moore, W. Luk, Eds., Lecture Notes in Computer Science 975 - Field-Programmable Logic and Applications, London: Springer, pp. 419-428, 1995.

.... applications, and support tools [Lysaght91, French93, Eldredge94, Lysaght94b, Koch94a, Razdan94, Ross94, Gokhale95, Hadley95, Jones95, Schoner95, DeHon96, Luk96, Villasenor96, Wittig96] Note that this approach can be taken even further to local run time reconfiguration [Lysaght94a, Singh94, Hutchings95, Brebner95, Lysaght95, Wirthlin95, Clark96, Wirthlin96] In a locally run time reconfigurable system different phases of an algorithm can have mappings to just a portion of the FPGA. Multiple configurations can be loaded into the system, with each configuration occupying different portions of the ....

B. L. Hutchings, M. J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Applications", in W. Moore, W. Luk, Eds., Lecture Notes in Computer Science 975 - Field-Programmable Logic and Applications, London: Springer, pp. 419-428, 1995.

....automatons. By providing FSM optimization and control over placement, our design environment enables the maximization of performance. 1 Introduction Reconfiguration models used in configurable computing can be classified into compile time reconfiguration (CTR) and run time reconfiguration (RTR) [6]. In CTR, the hardware compilation and the reconfiguration are done at compile time. At run time, the circuit loaded onto a reconfigurable resource is executed for many sets of input data. In RTR, the configuration of the reconfigurable resource is changed while the application is running. Here, ....

Brad L. Hutchings and Michael J. Wirthlin. Implementation Approaches for Reconfigurable Logic Applications. In International Workshop on Field-Programmable Logic and Applications (FPL), 1995.

....of a block of FPGA cells. With such facilities, it is possible to reconfigure each pipeline stage rapidly at run time to implement multiple functions. For a system operating in an unpredictable environment, this possibility enables the selection of functions adaptively. Partial reconfiguration [4] is a powerful method of exploiting the flexibility of FPGAs such as the Xilinx 6200: one part of the FPGA can be reconfigured while other parts are continuing to function. Pipelines provide a simple but effective scheme for partial reconfiguration, since pipeline registers isolate one pipeline ....

B. Hutchings and M.J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Applications", in Field Programmable Logic and Applications, W. Moore and W. Luk (eds.), LNCS 975, Springer, 1995, pp. 419--428.

....Framework We strive to develop design tools for run time reconfiguration that will become standard in future synthesis systems. From experience, the desirable features for such tools include: ffl the ability to produce a wide range of implementations that are globally or locally reconfigurable [8], covering devices which provide special hardware for rapid reconfiguration; ffl support for simulating, optimising and validating designs at various levels of abstraction; ffl facilities assisting design reuse and performance analysis. This section outlines a framework that meets the above ....

B. Hutchings and M.J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Applications ", in Field Programmable Logic and Applications, W. Moore and W. Luk (eds.), LNCS 975, Springer, 1995, pp. 419--428.

....broadest sense of the term, all systems with the capability of being reconfigured in circuit are dynamically reconfigurable. However, distinctions can be made between different types of dynamically reconfigurable systems. For example, most systems can be considered as compile time reconfigurable[36]. In other words, the hardware configuration for an application is determined at compile time and does 12 not change for the duration of the application [30] 29] Any dynamically reconfigurable system can be used in this fashion; however, some systems have even more flexibility. In fact, some ....

....change for the duration of the application [30] 29] Any dynamically reconfigurable system can be used in this fashion; however, some systems have even more flexibility. In fact, some define compile time RCs as static since their configuration does not change during the execution of an application[36]. Systems that change their hardware configuration during the execution time of the application can be thought of as run time reconfigurable [6] For example, RRANN I and II [20] 30] and ACME [46] are neural network based RCs. Since the training phase of a neural network can be broken into three ....

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B. L. Hutchings and M. J. Wirthlin. Implementation Approaches for Reconfigurable Logic Applications. In W. Moore and W. Luk, editors, Field-Programmable Logic and Applications, pages 419--428, Oxford, England, August 1995. Springer.

....unit of reconfiguration introduces a design abstraction that enables the development families of upwardly compatible FPGAs and virtual hardware design. 1. 0 Introduction Run time reconfiguration (RTR) has the potential to greatly increase the performance and applicability of FPGA based computing [3]. There are two significant problems inhibiting the deployment of applications based on RTR. First, design methodologies for partially reconfigured applications, or local RTR, are completely ad hoc. Second, existing FPGAs lack reconfiguration mechanisms that adequately support local RTR. Many of ....

....of each implementation technique. K T K NT ( 3.1 Component level Reconfiguration Using component level reconfiguration, the N different FPGA configurations from the N FPGA design are used to configure a single FPGA. This level of reconfiguration has also been called Global RTR in [3]. The configuration controller loads one configuration, and allows the FPGA to perform operations on pieces of data. It takes cycles to get the first result from this configuration, and cycles to get the remaining results. Therefore, the time required to complete these computations, in seconds, ....

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B. L. Hutchings and M. J. Withlin, "Implementation Approaches for Reconfigurable Logic Applications," in Field-Programmable Logic and Applications, FPL `95, pp. 419-428, Oxford, 1995.

....the first implementation of the DISC processor based on FPGAs. Section 2.2.1 describes the changes necessary to enable DISC to support C code. Those interested in understanding the hardware implementation of DISC in more detail than presented here are referred to the work by Hutchings and Wirthlin[17]. 2.2.1 DISC Hardware Environment The DISC processor was implemented on a custom PC ISA board with two run time reconfigurable[10] CLAy31[29, 28] chips, static bus interface circuitry and memory (see Figure 2.2) The first chip controls the configuration, processor execution and instruction ....

B. L. Hutchings and M. J. Wirthlin. Implementation Approaches for Reconfigurable Logic Applications. In W. Moore and W. Luk, editors, FieldProgrammable Logic and Applications, pages 419--428, Oxford, England, August 1995. Springer.

....of efficiency and performance provided by architectural specialization can be extended by specializing a computing architecture at runtime. Such dynamic circuit specialization is possible by reconfiguring the FPGA resources at run time. This technique, often called run time reconfiguration (RTR) [23, 24], provides additional opportunities for circuit specialization that are unavailable within static systems. Several CCM applications demonstrate improved hardware efficiency by specializing circuits at run time. A neural network application, for example, 3 increases the efficiency of its FPGA ....

B. L. Hutchings and M. J. Wirthlin. Implementation approaches for reconfigurable logic applications. In W. Moore and W. Luk, editors, FieldProgrammable Logic and Applications, pages 419--428, Oxford, England, August 1995. Springer-Verlag.

....constant propagated operators cannot be used and the advantages of constant propagation are not available. With dynamically configurable hardware, however, arbitrary input values can be supported by reconfiguring constantpropagated operators at run time. A form of run time reconfiguration (RTR) [11], this technique allows circuits to achieve the advantages of constant propaga tion while preserving the ability to support any arbitrary input value. Run time reconfiguration of constants is not a new technique several working systems have been designed to demonstrate this concept. Such ....

B. L. Hutchings and M. J. Wirthlin. Implementation approaches for reconfigurable logic applications. In W. Moore and W. Luk, editors, FieldProgrammable Logic and Applications, pages 419-- 428, Oxford, England, August 1995. Springer.

....[1, 2] One major benefit of SRAM FPGAs that is not often exploited is the ability to reconfigure the device during execution of the application. This technique, known as Run Time Reconfiguration (RTR) is used to provide additional hardware resources for systems based on reconfigurable FPGAs[3]. Using RTR, two neural network systems were developed to operate on far fewer FPGAs than their statically configured counterparts[4, 5] In addition, a wireless video This work was supported by ARPA CSTO under contract number DABT63 94 C 0085 under a subcontract to National Semiconductor. ....

....into equally sized temporal partitions. Partitioning in time requires the additional complexity of communicating between temporal partitions. In addition, systems employing RTR must tolerate the high time penalty required for configuration at run time. The Dynamic Instruction Set Processor (DISC)[3] is a run time reconfigured processor designed with FPGAs to exploit the advantages of RTR while limiting the disadvantages discussed above. DISC provides a convenient method of sequencing application specific hardware. In addition, DISC allows the caching of hardware modules to reduce the ....

B. L. Hutchings and M. J. Wirthlin. Implementation approaches for reconfigurable logic applications. In W. Moore and W. Luk, editors, FieldProgrammable Logic and Applications, pages 419-- 428, Oxford, England, August 1995. Springer.

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B.L. Hutchings and M.J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Application", FPL`95, pp.419-428,Oxford,1995.

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