S. Simovich, S. Mehrotra, P. Franzon, and M. Steer. Delay and reflection noise macromodeling for signal integrity management of pcbs and mcms. IEEE Trans. on CPMT, 17(1):15-21, 1994. Home/Search Document Details and Download
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Wire Length and Width Bound Generation for High-Speed MCM.. - Haizhou Chen Quad (Correct)
....and signal integrity violations and shorten design cycle. 2 Previous Works There are a few publications stating computation of bounds as their goal. In [1] multiple simulations are performed to determine the so called wiring rules that define the limits of line lengths and loads. 2] and [3] describe a general procedure of conversion from noise and timing constraints into line length. 4] proposes a framework for VLSI interconnection simulation, sensitivity analysis and optimization. In [5] a methodology is proposed to translate timing requirement into bounds on line length for ....
S. Simovich, S. Mehrotra, P. Franzon, and M. Steer, "Delay and reflection noise macromodeling for signal integrity management of PCBs and MCMs", IEEE Trans. on Components, Packaging and Manufacturing Technology-Part B: Advanced Packaging, Vol. 17, No. 1, pp. 15-21, 1994. net # delay(ns) \Delta delay overshoot(v) \Delta overshoot
Performance Driven Global Routing and Wiring Rule.. - Mehrotra, Franzon, Steer (1995) (2 citations) Self-citation (Mehrotra Franzon Steer) (Correct)
....5 Rule Generation Wiring Rules are explicit constraints on the geometry of the net, for example, a maximum and minimum constraint on each branch in the routing tree. If the electrical performance can be captured in a piece wise linear function, then the wiring rule can be generated directly [13]. However, such a global rule tends to be fairly conservative and does not lead to routing completion [14] The global routing solution gives a good starting point for wiring rule generation as it gives a minimum length that is highly likely to produce a feasible route. If the global route is ....
....global routed length for these nets did not meet the delay constraint. The reason for this is that the edge lengths in this graph were such that they may overestimate the actual routed lengths in some cases. The efficacy of the design rules was measured by the safeness coefficient, as described in [13]. Almost all design rules were 100 safe, with the worst coefficient being 72 . For more details, please see [10] Table 3: Constraints for Intel Pentium Design Net Class Design Space (m) Delay (ns) Pentium PCMC i 0.0 lo .165 7.49 PCMC Pentium I .058 lo .12 7.82 PCMC LBX 0.0 lo ....
S. Simovich, S. Mehrotra, P. Franzon, and M. Steer. Delay and reflection noise macromodeling for signal integrity management of pcbs and mcms. IEEE Trans. on CPMT, 17(1):15-21, 1994.
Global Optimization Approach to Transistor Sizing for.. - Mehrotra, Franzon, Liu (1993) Self-citation (Mehrotra Franzon) (Correct)
....the true objective and the constraint in a single objective function, then the optimization task is a little more difficult, as the overall model might have to account for disparate variations. Alternatively, the constraint can be modeled piece wise linearly by performing a separate experiment [16]. Then the optimization task is considerably simpler. The choice of method depends on the severity of the constraints. For a very tight constraint, it makes sense to pay close attention to the constraining function and use the first of the above approaches. For a loose constraint, the second ....
S. Simovich, S. Mehrotra, P. Franzon, and M. Steer. Delay and reflection noise macro- modeling for signal integrity management of PCBs and MCMs. IEEE Transactions on Components, Packaging and Manufacturing Technology, to appear in, 1993.
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