C.-T. Chou, J.-L. Huang and M.Fujita, A highlevel language for programming complex temporal behaviours and its translation into synchronous circuits, September 1996. Home/Search Document Details and Download
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A Calculus of Signals - Ratzko, Sanders (2000) (Correct)
....of conjunction and disjunction the theory of partial integration on which Schwartz s theory is based trivialises completely. Many of the established models for hardware design include timing; for a typical cross section we refer to RUBY [17] CIRCAL [23] HOL [5, 21] and various other languages [7, 8, 14]. Several of the commercial systems have semantic models; important examples are VHDL [3, 19] and Verilog [15, 11, 31, 1, 32, 24] There is also an established history of the use of temporal logic to study the timing aspects of hardware, for instance [10, 2, 22, 29, 20] and process algebra has ....
C.-T. Chou, J.-L. Huang and M.Fujita, A highlevel language for programming complex temporal behaviours and its translation into synchronous circuits, September 1996.
The Mathematical Foundation of Symbolic Trajectory Evaluation - Chou (1999) (9 citations) Self-citation (Chou) (Correct)
....it and use it on real world circuits. For specifying properties of hardware, which are usually highly parallel, one would like to have powerful parallel programming constructs in order to express the finitestate machine part of the trajectory assertion in an elegant manner. Our past experience [2] shows that synchronous languages [1, 5] may provide such constructs. Furthermore, programs in synchronous languages can be automatically translated into finite state machines in the form of circuits, which are then readily representable by BDDs [1, 2] Given our observation that STE is a form of ....
....in an elegant manner. Our past experience [2] shows that synchronous languages [1, 5] may provide such constructs. Furthermore, programs in synchronous languages can be automatically translated into finite state machines in the form of circuits, which are then readily representable by BDDs [1, 2]. Given our observation that STE is a form of DFA, two natural questions arise. First, is there anything in the vast literature on DFA [8] that is useful to STE Conversely, since most traditional DFA algorithms operate on bit vectors [8] could some forms of BDD based algorithms (such as our STE ....
Ching-Tsun Chou, Jiun-Lang Huang, and Masahiro Fujita, "A High-Level Language for Programming Complex Temporal Behaviors and Its Translation into Synchronous Circuits", poster presentation, IFIP Conference on Hardware Description Languages, Apr. 1997.
Synchronous Verilog: A Proposal - Ching-Tsun Chou Fujitsu Self-citation (Chou) (Correct)
....make it an attractive approach to the functional design of synchronous hardware. First, many powerful control constructs, such as concurrency, sequencing, iteration, preemption, suspension, and even a form of temporal abstraction, can be elegantly defined in the synchronous model of computation [1, 3]. Second, there exist natural syntax directed translations for implementing these constructs in ideal synchronous circuits (which are synchronous circuits whose combinational logic is truly infinitely fast) 2, 3] Therefore, by using a synchronous language (which is a programming language whose ....
.... abstraction, can be elegantly defined in the synchronous model of computation [1, 3] Second, there exist natural syntax directed translations for implementing these constructs in ideal synchronous circuits (which are synchronous circuits whose combinational logic is truly infinitely fast) [2, 3]. Therefore, by using a synchronous language (which is a programming language whose underlying model of computation is synchronous) with a rich set of control constructs, one can design synchronous hardware more by specifying temporal behavior and less by devising spatial structure. 2.2 Verilog ....
Ching-Tsun Chou, Jiun-Lang Huang, and Masahiro Fujita, "A HighLevel Language for Programming Complex Temporal Behaviors and Its Translation into Synchronous Circuits", poster presentation at IFIP Conf. on Computer Hardware Description Languages and Their Applications (CHDL'97), Toledo, Spain, 20--25 April 1997.
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